LAPIS Semiconductor ML62Q1000 Series User Manual page 226

Bit No. Bit symbol name
3,2 ILSIU10H, ILSIU10L
1,0 ILI2CU0H, ILI2CU0L
[Note]
Ÿ
Write to this register when the interrupt is disabled (IE0 to IE7 registers are "0x00") or the master
interrupt enable flag (MIE) is "0", otherwise, an interrupt may occur with an unexpected interrupt level.
FEUL62Q1000
This bit chooses the priority level of the Serial Communication unit 10 interrupt
(SIU10INT).
00: Level 1 (Priority is lowest) (initial)
01: Level 2
10: Level 3
11: Level 4 (Priority is highest)
This bit chooses the priority level of the I
00: Level 1 (Priority is lowest) (initial)
01: Level 2
10: Level 3
11: Level 4 (Priority is highest)
ML62Q1000 Series User's Manual
Description
2
C Bus unit 0 interrupt (I2CU0INT).
Chapter 5 Interrupts
5-30