LAPIS Semiconductor ML62Q1000 Series User Manual page 733

Figure 25-4 shows the flow diagram for programming the data flash area.
Start data flash programming
Enable programming flash
NO
When interrupt not used
YES
End programming data flash
NO
[Note]
Ÿ
The CPU continues program processing even while data flash programming is in progress. Do not enter
the STOP mode, STOP-D mode or HALT-H mode during the programming. In addition, set the FSELF bit
of the FLASHSLF register to "0" (erase/program disabled) after the programming ended.
Ÿ
The data flash area is unreadable during programming.
Ÿ
For data programming setting, place two NOP instructions following the instruction used to set the
programming data in the FLASHD0L register.
FEUL62Q1000
System clock setting
Interrupt setting, EI
(2)
FLASHSTA=0x00?
YES
Flash acceptor setting
Flash address setting
Write data setting
Start programming in background
Go to (4)
Continue
Programming?
NO
End
FLASHSTA=0x00?
YES
Disable flash write
Verify
End
Figure 25-4 Flow Diagram for Programming Data Flash Area
Set the high-speed clock for the system clock through the
FCON register
If using interrupts, execute MCINTEL.2=1, IE2.2=1, and EI.
FSELF = 1 MCINTEL:MCU status interrupt enable register
MCISTATL:MCU status interrupt register
MCINTCL: MCU status interrupt clear register
IE2: Interrupt enable register 2
Confirm the data flash state
FLASHACP = 0xFA
FLASHACP = 0xF5
FLASHSEG = 0x1F
FLASHAR = Address to be erased
FLASHD0L = Write data
" "
__asm( NOP );
__asm("NOP");
When interrupt used
Confirm the data flash state
FSELF = 0
ML62Q1000 Series User's Manual
Chapter 25 Flash Memory
Interrupt wait
Using MCISTATL
confirm interrupt source
Using MCISTATL
clear interrupt source
Go to (4)
See Chapter 5 "Interrupts" and
Sections 29.2.7 to 2.9 in Chapter 29
"Safety Function" for using
interrupts.
25-19