LAPIS Semiconductor ML62Q1000 Series User Manual page 429

Bit symbol
Bit no.
name
7 Un0RSS
6 to 3 -
2,1 Un0CK1 to
Un0CK0
0 Un0IO
[Note]
Ÿ
Be sure to set the UAn0MOD register while communication is stopped. Do not rewrite it during
communication. If it is rewritten during communication, data may be transmitted or received incorrectly.
FEUL62Q1000
This bit is used to choose sampling timing of the reception data in UARTn0 full-duplex and
half-duplex mode.
0: (Values set to UAn0BRTH and UAn0BRTL registers)/2 (initial value)
1: {(Values set to UAn0BRTH and UAn0BRTL registers)/2} -1
Reserved bit
This bit is used to choose base clock of baud rate generator in UARTn0 full-duplex and
half-duplex mode.
00: LSCLK (initial value)
01: Do not use (LSCLK)
10: HSCLK
11: Do not use (HSCLK)
This bit is used to choose the transmission mode or reception mode in UARTn0 full-duplex
and half-duplex mode. When the full-duplex communication mode is chosen, this bit is fixed
to "1" and the UART performs as the reception mode.
0: Transmission mode (Initial value)
1: Reception mode
ML62Q1000 Series User's Manual
Chapter 11 Serial Communication Unit
Description
11-27