LAPIS Semiconductor ML62Q1000 Series User Manual page 393

[Note]
Ÿ
Maximum of two clocks of WDTCLK are required during the period between writing "0x5A", "0xA5" to
the WDTCON register and clearing of the WDT counter. To enter the STOP mode or STOP-D mode
following WDT clearing, do so after making sure that the WDTCLR1 bit became "0".
In addition, if changing the WDTMOD register setting, write to the WDTMOD register after confirming
that both of WDTCLR1 and WDTCLR2 bits became "0" as soon as the WDT counter was cleared.
Ÿ
In the STOP/STOP-D mode, the WDT timer is stopped.
FEUL62Q1000
ML62Q1000 Series User's Manual
Chapter 10 Watchdog Timer
10-11