LAPIS Semiconductor ML62Q1000 Series User Manual page 502

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13.2.7 I C Master n Status Register (I2MnSTR: n=0,1)
I2MnSTR is a special function register (SFR) to indicate the state of the I
Address: 0xF6EC(I2M0STAT/I2M0STR), 0xF6ED(I2M0ISR)
0xF6FC(I2M1STAT/I2M1STR), 0xF6FD(I2M1ISR)
Access: R/W
Access size: 8/16bit
Initial value: 0x00
15 14
Word
Byte
- -
Bit
R/W R R
Initial
0 0
value
Bit
Bit symbol
name
No.
15 to
-
11
10 I2MnSPS
9 I2MnDS
8 I2MnAS
7 I2MnBO
6 to 3 -
2 I2MnER
FEUL62Q1000
13 12 11 10
I2MnISR
I2MnS
- - -
PS
R R R R/W
0 0 0 0
Reserved bit
This bit is used to indicate the usage state of the I
This bit is set to "1" when transmitting the stop condition has been completed on the I
To reset this bit, write "1" to this bit or write "0" to I2MnEN bit.
0: The stop condition has not been transmitted (Initial value)
1: The stop condition has been transmitted
This bit is used to indicate the usage state of the I
This bit is set to "1" when transmitting data or receiving data has been completed on the I
bus.
To reset this bit, write "1" to this bit or write "0" to I2MnEN bit.
0: The transmission/reception has not been completed (Initial value)
1: The transmission/reception has been completed
This bit is used to indicate the usage state of the I
This bit is set to "1" when transmitting the start condition and 7 bit slave address have been
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completed on the I C bus.
To reset this bit, write "1" to this bit or write "0" to I2MnEN bit.
0: The start condition and the slave address have not been transmitted (Initial value)
1: The start condition and the slave address have been transmitted
This bit is used to indicate the usage state of the I
This bit is set to "1" when transmitting the start condition has been completed and is reset to
"0" when the time (t
BUF
data communication error on the I2CMn_SDA pin.
When this bit is "1", it means the master has acquired use right of the I
To reset this bit, write "1" to this bit or write "0" to I2MnEN bit.
0: The use right of the I
1: The use right of the I
Reserved bit
This bit is used to indicate a transmission error.
When a bit of transmission data and the value on the I2CMn_SDA pin do not coincide, "1" is
set to this bit.
When this bit is set to "1" and the clock stretch function is used (I2MnSYN = "1"), the
I2Mn_SDA pin output is disabled until the subsequent byte data communication terminates.
Even if this bit is set to "1", the I2Mn_SDA pin output continues until the subsequent byte data
2
9 8 7 6
I2MnSTR
I2MnD I2MnA I2MnB
-
S S O
R/W R/W R/W R
0 0 0 0
Description
) has passed after transmitting the stop condition or there happened a
2
C bus has not been acquired (Initial value)
2
C bus has been acquired
ML62Q1000 Series User's Manual
Chapter 13 I2C Master
C bus unit in the master mode.
5 4 3 2
I2MnSTAT
I2MnE
- - -
R
R R R R/W
0 0 0 0
2
C bus.
2
C bus.
2
C bus.
2
C bus.
2
C bus.
1 0
I2MnA I2MnB
CR B
R/W R/W
0 0
2
C bus.
2
C
13-11