LAPIS Semiconductor ML62Q1000 Series User Manual page 864

See Section 6.2.3 "Low-speed Clock Mode Register (FLMOD)".
[ ] Do not change the LOSCM1 bit ad LOSCM0 bit when the ENOSC bit is "1", otherwise the operation is
unguaranteed.
[ ] Set PADXT0 pin and PADXT1 pin to the Hi-Z output mode when choosing the Low-speed crystal
oscillation clock for the low-speed clock.
See Section 6.2.4 "Clock Control Register (FCON)".
[ ] ENOSC bit and SELSCLK bit are forcibly set to "1" after releasing the HALT-H mode.
See Section 6.2.6 "See Section 6.2.4 "Clock Control Register (FCON)".
[ ] Operation for writing "0" to the LOSCB bit is ignored.
[ ] Insert two NOP instructions in the next to the instruction of that writes "1" to the LOSCB bit, then
ensure to confirm the LOSCB bit is reset to "0" after that.
[ ] When switching to the low speed crystal oscillation clock, ensure to use the interrupt referring to the
Section 6.3.5 "Switching the Low-speed Clock".
See Section 6.2.7 "Backup Clock Status Register (FBUSTAT)".
[ ] In case the LOSCS bit gets to "1" after the LOSCB bit is set to "1", immediately set the mode back to
"Low-speed RC oscillation clock" by resetting the LOSCM[1:0] of FLMOD register to "00" and handle it
appropriately for the application.
[ ] Refer to the Section 6.3.5 "Switching the Low-speed Clock" to control the LOSCS bit.
See Section 6.2.9 "Clock Backup Test Mode (FBTCON)".
[ ] Use the clock backup test mode after setting the low-speed crystal oscillation clock mode.
See Section 6.2.10 "Low-Speed RC Oscillation Frequency Adjustment Register (LRCADJ)".
[ ] Use the RC oscillation adjustment sample software provided by LAPIS. Otherwise, the operation is not
guaranteed.
See Section 6.3.1.2 "Configuration of Low-Speed Crystal Oscillation Circuit".
[ ] Place the crystal resonator as close to the LSI as possible and make sure that signals causing noise
and power supply wiring are not near the crystal and its wiring.
[ ] Note that oscillation may stop due to condensation.
[ ] When switching to the low speed crystal oscillation clock, ensure to use the interrupt referring to the
Section 6.3.5 "Switching the Low-speed Clock".
[ ] When using the low-speed crystal oscillation clock and choosing the high-speed clock for the system
clock, switch the system clock to the high-speed clock before entering the STOP/STOP-D mode.
See Section 6.3.4 "Switching of System Clock".
[ ] When the voltage of VDD is 1.6 V ≤ VDD < 1.8 V, set the system clock (SYSTEMCLK) and the
high-speed clock (HSCLK) to 4 MHz or below. If it exceeds 4 MHz, the operation is not guaranteed.
[ ] While the CPU is running with the low-speed clock, if running the peripheral circuits with the
high-speed clock which can frequently generate interrupts, the operation may fail to function properly due
to the CPU becoming incapable of processing interrupts in time. If interrupts frequently occur for reasons
such as short interrupt cycles of peripheral circuits, take into account the operating frequency of the CPU
so that it can process interrupts in time.
Chapter 7 Low-speed Time Base Counter
See Section 7.2.2 "Low-speed Time Base Counter Operation".
[ ] A time base counter interrupt may occur depending on a write timing to the LTBR. See the program
example for initializing described in Section 7.3.1 "Operation of the Low-speed Time Base Counter".
[ ] T128HZ to T1HZ signals have "0" level in the first half cycle and "1" level in the last half. For example,
T1HZ signal gets reset to "0" by writing any data to LTBR and it get to "1" about 0.5sec later and returns
to "1" about 1sec later from the reset. The low-speed time base counter interrupt occurs at the falling
edge ("1" to "0") of the signal. See "Time base counter interrupt timing and reset timing of reset by writing
to LTBR" for details about the waveform of signal. See Figure 7-5 "Low speed time base counter
interrupt timing and reset timing of reset by writing to LTBR" for details of the T128Hz to T1Hz waveform.
[ ] When the high-speed clock is used for the system clock, read the LTBR register twice to verify the data
to prevent reading uncertain data while counting-up.
FEUL62Q1000
ML62Q1000 Series User's Manual
Appendix E. List of Notes
E-5