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ML610Q421
LAPIS Semiconductor ML610Q421 Manuals
Manuals and User Guides for LAPIS Semiconductor ML610Q421. We have
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LAPIS Semiconductor ML610Q421 manual available for free PDF download: User Manual
LAPIS Semiconductor ML610Q421 User Manual (437 pages)
Brand:
LAPIS Semiconductor
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Table of Contents
5
Chapter 1 Overview
15
Features
16
Configuration of Functional Blocks
20
Block Diagram of ML610Q421
20
Block Diagram of ML610Q422
21
Block Diagram of ML610421
22
Pins
23
Pin Layout
23
Pin Layout of ML610Q421 120Pin TQFP Package
23
Pin Layout of ML610Q422 120Pin TQFP Package
24
Pin Layout of ML610Q421 Chip
25
Pin Layout of ML610Q422 Chip
26
Pin Layout of ML610421 Chip
27
Pad Coordinates of ML610Q421 Chip
28
Pad Coordinates of ML610Q422 Chip
29
Pad Coordinates of ML610421 Chip
30
List of Pins
31
List of ML610Q421/ML610Q422 Pins
31
List of ML610421 Pins
35
Description of Pins
39
Termination of Unused Pins
43
Chapter 2 CPU and Memory Space
44
Overview
45
Program Memory Space
45
Data Memory Space
46
Instruction Length
46
Data Type
46
Description of Registers
47
List of Registers
47
Data Segment Register (DSR)
48
Chapter 3 Reset Function
49
Overview
50
Features
50
Configuration
50
List of Pin
50
Description of Registers
51
List of Registers
51
Reset Status Register RSTAT
51
Description of Operation
52
Operation of System Reset Mode
52
Chapter 4 MCU Control Function
53
Overview
54
Features
54
Configuration
54
Description of Registers
55
List of Registers
55
Stop Code Acceptor (STPACP)
56
Standby Control Register (SBYCON)
57
Block Control Register 0(BLKCON0)
58
Block Control Register 1(BLKCON1)
59
Block Control Register 2(BLKCON2)
60
Block Control Register 3(BLKCON3)
61
Block Control Register 4(BLKCON4)
62
Description of Operation
64
Program Run Mode
64
HALT Mode
64
STOP Mode
65
STOP Mode When CPU Operates with Low-Speed Clock
65
STOP Mode When CPU Operates with High-Speed Clock
66
Note on Return Operation from STOP/HALT Mode
67
Block Control Function
68
Chapter 5 Interrupts (Ints)
69
Overview
70
Features
70
Description of Registers
71
List of Registers
71
Interrupt Enable Register 1 (IE1)
72
Interrupt Enable Register 2 (IE2)
73
Interrupt Enable Register 3 (IE3)
74
Interrupt Enable Register 4 (IE4)
75
Interrupt Enable Register 5 (IE5)
76
Interrupt Enable Register 6 (IE6)
77
Interrupt Enable Register 7 (IE7)
78
Interrupt Request Register 0 (IRQ0)
79
Interrupt Request Register 1 (IRQ1)
80
Interrupt Request Register 2 (IRQ2)
81
Interrupt Request Register 3 (IRQ3)
82
Interrupt Request Register 4 (IRQ4)
83
Interrupt Request Register 5 (IRQ5)
84
Interrupt Request Register 6 (IRQ6)
85
Interrupt Request Register 7 (IRQ7)
86
Description of Operation
87
Maskable Interrupt Processing
88
Non-Maskable Interrupt Processing
88
Software Interrupt Processing
88
Notes on Interrupt Routine
89
Interrupt Disable State
92
Chapter 6 Clock Generation Circuit
93
Overview
94
Features
94
Configuration
94
List of Pins
95
Description of Registers
95
List of Registers
95
Frequency Control Register 0 (FCON0)
96
Frequency Control Register 1 (FCON1)
98
Description of Operation
99
Low-Speed Clock
99
Low-Speed Clock Generation Circuit
99
Operation of Low-Speed Clock Generation Circuit
100
High-Speed Clock
101
500 Khz RC Oscillation
101
Crystal/Ceramic Oscillation Mode
102
Built-In PLL Oscillation Mode
103
External Clock Input Mode
103
Operation of High-Speed Clock Generation Circuit
104
Switching of System Clock
106
Specifying Port Registers
108
Functioning P21 (OUTCLK) as the High Speed Clock Output
108
Functioning P20 (LSCLK) as the Low Speed Clock Output
109
Chapter 7 Time Base Counter
110
Overview
111
Features
111
Configuration
111
Description of Registers
113
List of Registers
113
Low-Speed Time Base Counter (LTBR)
114
High-Speed Time Base Counter Divide Register (HTBDR)
115
Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH)
116
Description of Operation
117
Low-Speed Time Base Counter
117
High-Speed Time Base Counter
118
Low-Speed Time Base Counter Frequency Adjustment Function
119
A Signal Generation for 16Bit Timer 2-3 Frequency Measurement Mode
120
Chapter 8 Capture
121
Overview
122
Features
122
Configuration
122
List of Pins
122
Description of Registers
123
List of Registers
123
Capture Control Register (CAPCON)
124
Capture Status Register (CAPSTAT)
125
Capture Data Register 0 (CAPR0)
126
Capture Data Register 1 (CAPR1)
127
Description of Operation
128
Chapter 9 Khz Timer (1Khztm)
129
Overview
130
Features
130
Configuration
130
Description of Registers
131
List of Registers
131
Khz Timer Count Registers (T1KCRL, T1KCRH)
132
Khz Timer Control Register (T1KCON)
133
Description of Operation
134
Chapter 10 Timers
135
Overview
136
Features
136
Configuration
136
Description of Registers
138
List of Registers
138
Timer 0 Data Register (TM0D)
139
Timer 1 Data Register (TM1D)
140
Timer 2 Data Register (TM2D)
141
Timer 3 Data Register (TM3D)
142
Timer 0 Counter Register (TM0C)
143
Timer 1 Counter Register (TM1C)
144
Timer 2 Counter Register (TM2C)
145
Timer 3 Counter Register (TM3C)
146
Timer 0 Control Register 0 (TM0CON0)
147
Timer 1 Control Register 0 (TM1CON0)
148
Timer 2 Control Register 0 (TM2CON0)
149
Timer 3 Control Register 0 (TM3CON0)
150
Timer 0 Control Register 1 (TM0CON1)
151
Timer 1 Control Register 1 (TM1CON1)
152
Timer 2 Control Register 1 (TM2CON1)
153
Timer 3 Control Register 1 (TM3CON1)
154
Description of Operation
155
Timer Mode Operation
155
16-Bit Timer Frequency Measurement Mode Operation
156
16-Bit Timer Frequency Measurement Mode Application for Setting Uart Baud-Rate
158
Chapter 11 PWM
160
Overview
161
Features
161
Configuration
161
List of Pins
162
Description of Registers
162
List of Registers
162
PWM0 Period Registers (PW0PL, PW0PH)
163
PWM0 Duty Registers (PW0DL, PW0DH)
164
PWM0 Counter Registers (PW0CH, PW0CL)
165
PWM0 Control Register 0 (PW0CON0)
166
PWM0 Control Register 1 (PW0CON1)
167
Description of Operation
168
Specifying Port Registers
170
Functioning P43 (PWM0) as the PWM Output
170
Functioning P34 (PWM0) as the PWM Output
171
Chapter 12 Watchdog Timer
172
Overview
173
Features
173
Configuration
173
Description of Registers
174
List of Registers
174
Watchdog Timer Control Register (WDTCON)
175
Watchdog Timer Mode Register (WDTMOD)
176
Description of Operation
177
Handling Example When You Do Not Want to Use the Watch Dog Timer
179
Chapter 13 Synchronous Serial Port
180
Overview
181
Features
181
Configuration
181
List of Pins
182
Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH)
184
Serial Port Control Register (SIO0CON)
185
Serial Port Mode Register 0 (SIO0MOD0)
186
Serial Port Mode Register 1 (SIO0MOD1)
187
Description of Operation
188
Transmit Operation
188
Receive Operation
189
Transmit/Receive Operation
190
Specifying Port Registers
191
Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ "Master Mode
191
Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ "Slave Mode
192
Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ "Master Mode
193
Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ "Slave Mode
194
Chapter 14 UART
195
Overview
196
Features
196
Configuration
196
List of Pins
196
Description of Registers
197
List of Registers
197
UART0 Transmit/Receive Buffer (UA0BUF)
198
UART0 Control Register (UA0CON)
199
UART0 Mode Register 0 (UA0MOD0)
200
UART0 Mode Register 1 (UA0MOD1)
201
UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH)
203
UART0 Status Register (UA0STAT)
204
Description of Operation
206
Transfer Data Format
206
Baud Rate
207
Transmit Data Direction
208
Transmit Operation
209
Receive Operation
211
Specifying Port Registers
213
Functioning P43(TXD0) and P42(RXD0) as the UART
213
Functioning P43(TXD0) and P02(RXD0) as the UART
214
Chapter 15 I 2 C Bus Interface
216
Overview
217
Features
217
Configuration
217
List of Pins
217
Description of Registers
218
List of Registers
218
I 2 C Bus 0 Receive Register (I2C0RD)
219
I 2 C Bus 0 Slave Address Register (I2C0SA)
220
I 2 C Bus 0 Transmit Data Register (I2C0TD)
221
I 2 C Bus 0 Control Register (I2C0CON)
222
I 2 C Bus 0 Mode Register (I2C0MOD)
223
I 2 C Bus 0 Status Register (I2C0STAT)
224
Description of Operation
225
Communication Operating Mode
225
Start Condition
225
Repeated Start Condition
225
Slave Address Transmit Mode
225
Data Transmit Mode
225
Data Receive Mode
225
Control Register Setting Wait State
225
Stop Condition
226
Communication Operation Timing
227
Operation Waveforms
229
Specifying Port Registers
230
Functioning P41(SCL) and P40(SDA) as the I2C
230
Chapter 16 NMI Pin
231
Overview
232
Features
232
Configuration
232
List of Pins
232
Description of Registers
233
List of Registers
233
NMI Data Register (NMID)
234
NMI Control Register (NMICON)
235
Description of Operation
236
Interrupt Request
236
Chapter 17 Overview
238
Features
238
Configuration
238
List of Pins
238
Port 0 Data Register (P0D)
240
Port 0 Control Registers 0, 1 (P0CON0, P0CON1)
241
External Interrupt Control Registers 0, 1 (EXICON0, EXICON1)
242
External Interrupt Control Register 2 (EXICON2)
243
Description of Operation
244
External Interrupt/Capture Function
244
Interrupt Request
244
Chapter 18 Overview
247
Features
247
Configuration
247
Port 1 Data Register (P1D)
249
Port 1 Control Registers 0, 1 (P1CON0, P1CON1)
250
Description of Operation
251
Input Port Function
251
Secondary Function
251
Chapter 19 Overview
253
Features
253
Configuration
253
List of Pins
253
Description of Registers
254
List of Registers
254
Port 2 Data Register (P2D)
255
Port 2 Control Registers 0, 1 (P2CON0, P2CON1)
256
Port 2 Mode Register (P2MOD)
257
Description of Operation
258
Output Port Function
258
Secondary Function
258
Chapter 20 Port 3
259
Overview
260
Features
260
Configuration
260
List of Pins
261
Description of Registers
262
List of Registers
262
Port 3 Data Register (P3D)
263
Port 3 Direction Register (P3DIR)
264
Port 3 Control Registers 0, 1 (P3CON0, P3CON1)
265
Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1)
267
Description of Operation
269
Input/Output Port Functions
269
Secondary and Tertiary Functions
269
Chapter 21 Port 4
270
Overview
271
Features
271
Configuration
271
List of Pins
272
Port 4 Data Register (P4D)
274
Port 4 Direction Register (P4DIR)
275
Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1)
278
Description of Operation
281
Input/Output Port Functions
281
Secondary and Tertiary Functions
281
Chapter 22 Port a
282
Overview
283
Features
283
Configuration
283
List of Pins
283
Description of Registers
284
List of Registers
284
Port a Data Register (PAD)
285
Port a Direction Register (PADIR)
286
Port a Control Registers 0, 1 (PACON0, PACON1)
287
Description of Operation
289
Input/Output Port Functions
289
Chapter 23 Melody Driver
290
Overview
291
Features
291
Configuration
291
List of Pins
291
Description of Registers
292
List of Registers
292
Melody 0 Control Register (MD0CON)
293
Melody 0 Tempo Code Register (MD0TMP)
294
Melody 0 Scale Code Register (MD0TON)
295
Melody 0 Tone Length Code Register (MD0LEN)
296
Description of Operation
297
Operation of Melody Output
297
Tempo Codes
298
Tone Length Codes
299
Scale Codes
300
Example of Using Melody Circuit
301
Operations of Buzzer Output
302
Specifying Port Registers
303
Functioning P22 (MD0) as the Melody or Buzzer Output
303
Chapter 24 RC Oscillation Type A/D Converter
304
Overview
305
Features
305
Configuration
305
RC-ADC Counter a Registers (RADCA0–2)
308
RC-ADC Counter B Registers (RADCB0–2)
309
RC-ADC Mode Register (RADMOD)
310
RC-ADC Control Register (RADCON)
311
Description of Operation
312
RC Oscillator Circuits
312
Counter A/Counter B Reference Modes
315
Example of Use of RC Oscillation Type A/D Converter
319
Monitoring RC Oscillation
324
Specifying Port Registers
325
Functioning P35(RCM), P34(RCT0), P33(RT0), P32(RS0), P31(CS0) and P30(IN0) as the RC-ADC(Ch0)
325
Functioning P47(RT1), P46(RS1), P45(CS1) and P44(IN1) as the RC-ADC(Ch1)
326
Chapter 25 Successive Approximation Type A/D Converter
327
Overview
328
Features
328
Configuration
328
List of Pins
329
Description of Registers
330
List of Registers
330
SA-ADC Result Register 0L (SADR0L)
331
SA-ADC Result Register 0H (SADR0H)
331
SA-ADC Result Register 1L (SADR1L)
332
SA-ADC Result Register 1H (SADR1H)
332
SA-ADC Control Register 0 (SADCON0)
333
SA-ADC Control Register 1 (SADCON1)
334
SA-ADC Mode Register 0 (SADMOD0)
335
Description of Operation
336
Operation of the Successive Approximation A/D Converter
337
Chapter 26 LCD Drivers
338
Overview
339
Features
341
Configuration of the LCD Drivers
342
Configuration of the Bias Generation Circuit
343
List of Pins
344
Description of Registers
347
List of Registers
347
Bias Circuit Control Register 0 (BIASCON)
348
Display Control Register (DSPCNT)
349
Display Mode Register 0 (DSPMOD0)
350
Display Mode Register 1 (DSPMOD1)
352
Display Control Register (DSPCON)
353
Display Allocation Register a (DS0C0A to DS49C7A)
354
Display Allocation Register B (DS0C0B to DS49C7B)
356
Display Registers (DSPR00 to DSPR71)
358
Description of Operation
363
Operation of LCD Drivers and Bias Generation Circuit
363
Segment Mapping When the Programmable Display Allocation Function Is Not Used
364
Segment Mapping When the Programmable Display Allocation Function Is Used
365
Common Output Waveforms
367
Segment Output Waveforms
369
Chapter 27 Battery Level Detector
371
Overview
372
Features
372
Configuration
372
Description of Registers
373
List of Registers
373
Battery Level Detector Control Register 0 (BLDCON0)
374
Battery Level Detector Control Register 1 (BLDCON1)
375
Description of Operation
376
Threshold Voltage
376
Operation of Battery Level Detector
377
Chapter 28 Power Supply Circuit
378
Overview
379
Features
379
Configuration
379
List of Pins
379
Description of Operation
380
Chapter 29 On-Chip Debug Function
381
Overview
382
Method of Connecting to On-Chip Debug Emulator
382
Flash Memory Rewrite Function
383
Appendixes
384
Appendix A Registers
385
Appendix B Package Dimensions
411
Appendix C Electrical Characteristics
418
Appendix D Application Circuit Example
429
Appendix E Check List
431
Revision History
435
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