LAPIS Semiconductor ML62Q1000 Series User Manual page 425

Bit symbol
Bit no.
name
7 to 4 -
3 SnLG
2 to 1 SnMD1 to
SnMD0
0 SnDIR
[Note]
Ÿ
Be sure to set the SIO0MOD register while communication is stopped and do not rewrite it during
communication. If it is rewritten during communication, data may be transmitted or received incorrectly.
Ÿ
Set the S0CK4 to S0CK0 bits to 4MHz or below.
Ÿ
Enable the high-speed oscillation when choosing the slave mode. See Chapter 6 "Clock
GenerationCircuit" for details on how to enable the high-speed oscillation.
Ÿ
The maximum frequency of communication clock is 1MHz in the slave mode.
FEUL62Q1000
Reserved bit
This bit is used choose the bit length of the transmission/reception data in the SSIO mode.
0: 8-bit length (initial value)
1: 16-bit length
This bit is used to choose the transmission/reception mode in the SSIO mode.
00: Transmit/Receive is stopped (initial value)
01: Receive mode
10: Transmit mode
11: Transmit/Receive mode
This bit is used to choose the communication direction in the SSIO mode.
0: LSB first (Initial value)
1: MSB first
ML62Q1000 Series User's Manual
Chapter 11 Serial Communication Unit
Description
11-23