LAPIS Semiconductor ML62Q1000 Series User Manual page 35

1.2.3
Block Diagram of
V
DD
V
SS
V
DDL
Power
Circuit
RESET_N
2
TEST0*
OUTLSCLK*
Generation
OUTHSCLK*
Low-speed
Oscillation
High-speed
Oscillation
Oscillation
(For WDT)
Low-speed
3
XT0*
3
XT1*
Oscillation
V
DD
V
SS
Converter
V *
REFI
AIN0 to AIN15*
CMP0-1P*
Comparator
CMP0-1M*
DACOUT0-1*
Converter
V ,V ,V
L1 L2 L3
C ,C
1 2
COM0-COM2
COM3-COM7/
SEG0-SEG4
SEG5-SEG61
* : Indicates the shared functions of general ports.
1
* : One channel Full-duplex UART is configurable as two channel Half-duplex UART.
2
* : Unavailable as the input port when connecting to the on-chip debug emulator(EASE1000).
3
* : Unavailable as the input port when connecting to the crystal resonator.
FEUL62Q1000
ML62Q1700 Group
CPU (nX-U16/100)
EPSW1-3
GREG
0 -15
PSW
ALU
Timing
Controller
Instruction
On-Chip Decoder
ICE
TEST
INT
Clock
Circuit
RC
INT
PLL
INT
RC
INT
Crystal
INT
A/D
INT
INT
Analog
INT
D/A
LCD
Bias
LCD
Driver
Figure 1-6 ML62Q1700 Group Block Diagram
ECSR1-3
ELR1-3
DSR/CSR
LR
PC
EA
SP
BUS
Controller
Instruction
Register
INT
RAM
Data Flash
FLASH
INT
Controller
INT
Interrupt
INT
INT
WDT
INT
VLS
DMA
Controller
INT
CRC
Generator
Simplified
RTC
INT
Safety
Function
Reset
Function
ML62Q1000 Group User's Manual
Chapter 1 Overview
Multiplier/Divider
(Coprocessor)
Program memory
(Flash)
SU0-5_SCLK*
SU0-5_SIN*
SU0-5_SOUT*
Serial
Unit
SU0-5_RXD0*
SU0-5_TXD0*
SU0-5_RXD1*
SU0-5_TXD1*
2
I C Bus
I2CU0_SDA*
Unit
I2CU0_SCL*
2
I C I2CM0-1_SDA*
Master I2CM0-1_SCL*
16bit
TMH0-7OUT*
Timer
EXTRIG0-7
16bit
FTM0-7P*
Function
FTM0-7N*
al Timer
TBCOUT0*
Time-base
Counter
TBCOUT1*
BZ0P*
Buzzer
BZ0N*
PX0-PX7
(X=0-9,A,B)
GPIO
PI00, PI01
(External
EXI0-11
Interrupt)
1
1
1
1
1-18