LAPIS Semiconductor ML62Q1000 Series User Manual page 866

See Section 8.2.7 "16-Bit Timer Start Register (TMHSTR)".
[ ] The bit 15 to 8 of TMHSTR register are not used in the 16-bit timer mode. Writing "1" to those bits are
ignored.
[ ] Set HnRUN/THnHRUN bits when the timer n is stopped(THnSTAT/THnHSTAT bits of TMHSTAT
register are "0").
See Section 8.2.8 "16-Bit Timer Stop Register (TMHSTP)".
[ ] The bit 15 to 8 of TMHSTP register are not used in the 16-bit timer mode. Writing "1" to those bits are
ignored.
[ ] Set THnSTP/THnHSTP bits when the timer n is running(THnSTAT/THnHSTAT bits of TMHSTAT
register are "1").
See Section 8.3.2.2 "One-shot Mode".
[ ] In the 8-bit timer mode, the timer output is only available by the upper side 8-bit timer.
See Section 8.3.3.1 "Start/Stop Timing".
[ ] Since counting operation is not suspended during the period in which THnSTAT bit is "1", restart of the
counting is ignored even if THnRUN bit is set to "1" in this period. To restart the counting, make sure that
the THnSTAT is set to "0", then set the THnRUN bit to "1".
[ ] After the THnRUN bit is set to "1", the first interrupt has a time error equivalent to maximum of one
clock of the timer clock because the counting operation starts in synchronization with the timer clock. The
2nd timer interrupt or later interrupts have constant cycles.
[ ] After the THnSTP bit is set to "1", a timer n interrupt (TMnINT) may be generated depending on the
stop timing because the counting operation stops in synchronization with the timer clock.
See Section 8.3.3.2 "External Input Count Timing".
[ ] The pulse with the width less than two clocks of the timer clock may be ignored. Always input the
external input signal with the width equal to or more than two clocks of the timer clock.
[ ] The external input signal (EXTRGn) which is input to the 16-bit timer is the signal that has passed the
sampling controller of the external interrupt function. The sampling of the external interrupt function is
optional. See Chapter 18 "External Interrupt Function" for details.
Chapter 9 Functional Timer
See Section 9.2.2 "FTMn Cycle Register (FTnP: n = 0 to 7)".
[ ] When 0x0000 is written in this register, 0x0001 is set and the read value is also becomes 0x0001.
See Section 9.2.3 "FTMn Event Register A (FTnEA: n = 0 to 7)".
[ ] The data set in the FTnEA register must be less than that set in the FTnP register in the TIMER mode
or PWM2 mode.
See Section 9.2.4 "FTMn Event Register B (FTnEB: n = 0 to 7)".
[ ] The data set in the FTnEB register must be less than that set in the FTnP register in the TIMER mode.
See Section 9.2.9 "FTMn Clock Register (FTnCLK: n=0 to 7)".
[ ] The pulse input to the EXTRG0 to EXTRG7 pin must have "the noise removal width chosen by
FTnTRF2 to 0 bits of FTnTRG1 register + two timer clocks" or longer.
See Section 9.2.10 "FTMn Trigger Register 0 (FTnTRG0: n = 0 to 7)".
[ ] The pulse input to the EXTRG0 to EXTRG7 pin must have "the noise removal width chosen by
FTnTRF2 to 0 bits of FTnTRG1 register + two timer clocks" or longer.
See Section 9.2.11 "FTMn Trigger Register 1 (FTnTRG1: n = 0 to 7)".
[ ] When using the COMP0D, EXTRG0 and EXTRG4 as the emergency stop trigger, the noise filter
function set by the FTnTRF2 to 0 bits of FTnTRG1 register are invalid. Use another filter function in each
peripheral module.
[ ] If a level setting is chosen for the condition of the counter start and condition is matched, the count
operation continues (restart the count-up from 0) even if a stop condition is satisfied in the one-shot
mode.
[ ] When using the EXTRG0 to EXTRG7, enable the trigger event after setting the noise filter by the
FTnTRG1 register. Otherwise, the trigger may occur immediately after setting the FTnTRG1 register.
FEUL62Q1000
ML62Q1000 Series User's Manual
Appendix E. List of Notes
E-7