LAPIS Semiconductor ML62Q1000 Series User Manual page 872

See Section 15.3.5.1 "Buzzer Output Start and Stop Timing".
[ ] An error to a maximum of one clock of the low-speed clock (LSCLK) occurs by the time the buzzer
output is started after writing "1" to the BZ0RUN bit of the BZ0CON register.
[ ] An error to a maximum of one clock of the low-speed clock (LSCLK) occurs by the time the buzzer
output is stopped after writing "0" to the BZ0RUN bit of the BZ0CON register.
[ ] In the single sound mode, the BZ0RUN bit of the BZ0CON register is cleared to "0" when the single
sound buzzer output is ended.
[ ] In the intermittent sound 1 or 2 mode, an error to a maximum of one clock of the low-speed clock
(LSCLK) occurs by the time the buzzer output is started after the T8HZ signal became "1".
Chapter 16 Simplified RTC
See Section 16.2.1 "List of Registers".
[ ] SRTCMAS is reset only by the power-on reset.
See Section 16.2.2 "Simplified RTC Acceptor (SRTCACP)".
[ ] After writing "0x3C" to SRTCACP, if data other than "0x3C" or "0xC3" is written to SRTCACP, writing of
"0x3C" becomes invalid.
[ ] When writing "0x3C" and "0xC3" to SRTCACP in this order, and writing a value other than "0xC3" to
SRTCACP with writing to SRTCMAS enabled, writing to SRTCMAS becomes invalid.
See Section 16.2.3 "Simplified RTC Minute/Second Counter (SRTCMAS)".
[ ] When reading the SRTCMAS register, read it twice and check that the two values coincide with each
other to prevent reading of undefined data during counting up.
[ ] If the data outside the range from 00 minutes 00 seconds to 59 minutes 59 seconds is written to the
SRTCMAS register, the register will be set to the initial value.
[ ] An interrupt request may be generated immediately after writing depending on the timing of writing
data to the SRTCMAS register. To prevent an interrupt request from being generated while writing time
data, disable the periodical interrupt request using the simplified RTC control register (SRTCCON)
before writing to the SRTCMAS register.
[ ] It is recommended that data is written to the SRTCMAS register with word access.
[ ] After enabling the write operation using the RTCACP register, data can be written to the SRTCMAS
register only once regardless of using byte or word access. If writing twice using 8-bit access after the
write operation is enabled, the second writing is ignored.
[ ] If 0 second (0x00) is written to the second counter (SRTCSEC) when it is 59 second (0x59), the minute
counter (SRTCMIN) counts up. However, if the minute counter is also written at the same time using
16-bit access, then it does not count up and the written value becomes valid.
Chapter 17 General Purpose Port
See Section 17.2.3 "Port n Mode Register 01 (PnMOD01:n＝0 to 9, A, B)".
[ ] Be sure to set the PnMODm(n＝0 to B, m=0 to 7) registers before setting EICON0, EIMOD0 and IE1
registers. If setting the PnMODm register when the interrupt is enabled, unexpected interrupts may
happen.
[ ] Enable the output by setting the PnmOE bit after the following configuration.
In the case of general ports: Determine the output data in the PnmDO bit of PnD register.
In the case of shared functions: Configure the peripheral mode settings in the PnmMD3 to PnmMD0 bit.
See Section 17.2.9 "PORTXT data input register (PXTDI)".
[ ] PI00 and PI01 are unavailable to use as input ports when using the crystal resonator for the oscillation
clock. Also, PI01 is unavailable to use as an input port when using the PI01 for the external clock input.
See Chapter 6 "Clock Generation Circuit" for more details on how to use the crystal oscillation or external
clock input.
See Section 17.3.8 "Notes for using the P00/TEST0 pin".
[ ] The P00/TEST0 is initially configured as the input with pull-up register. If input "L" level at the initial
setting, the input current flows.
[ ] When using the on-chip debug function or ISP function, P00/TEST0 is unavailable to use as the
general purpose port.
- Do not program the software that makes the P00/TEST0 pin output mode.
- Do not connect external components onto the P00/TEST0 pin.
FEUL62Q1000
ML62Q1000 Series User's Manual
Appendix E. List of Notes
E-13