LAPIS Semiconductor ML62Q1000 Series User Manual page 10

10.2.3 Watchdog Timer Mode Register (WDTMOD) .......................................................................................... 10-6
10.2.4 Watchdog Timer Counter Register (WDTMC) ......................................................................................... 10-7
10.2.5 Watchdog Status Register (WDTSTA) ...................................................................................................... 10-8
10.3 Description of Operation ........................................................................................................................... 10-9
10.3.1 How to Clear WDT Counter .................................................................................................................... 10-10
10.3.2 Window Function Disabled Mode ........................................................................................................... 10-12
10.3.3 Window Function Enabled Mode ............................................................................................................ 10-16
Chapter 11
11. Serial Communication Unit .......................................................................................................................... 11-1
11.1 General Description ................................................................................................................................... 11-1
11.1.1 Features ...................................................................................................................................................... 11-1
11.1.2 Configuration ............................................................................................................................................. 11-3
11.1.3 List of Pins ................................................................................................................................................. 11-4
11.1.4 Combination of SSIO port ......................................................................................................................... 11-8
11.1.5 Combination of UART port ....................................................................................................................... 11-8
11.2 Description of Registers ............................................................................................................................. 11-9
11.2.1 List of Registers ......................................................................................................................................... 11-9
11.2.2 Serial Communication Unit n Transmit/Receive Buffer (SDnBUF) ....................................................... 11-16
11.2.3 Serial Communication Unit n Mode Register (SUnMOD) ...................................................................... 11-18
11.2.4 Serial Communication Unit n Transmission Interval Setting Register (SUnDLY) ................................. 11-19
11.2.5 Serial Communication Unit n Control Register (SUnCON) .................................................................... 11-21
11.2.6 Synchronous Serial Port n Mode Register (SIOnMOD) .......................................................................... 11-22
11.2.7 Synchronous Serial Port n Status Register (SIOnSTAT) ......................................................................... 11-24
11.2.8 UARTn0 Mode Register (UAn0MOD) ................................................................................................... 11-26
11.2.9 UARTn1 Mode Register (UAn1MOD) ................................................................................................... 11-28
11.2.10 UARTn0 Baud Rate Register (UAn0BRT) ........................................................................................... 11-30
11.2.11 UARTn1 Baud Rate Register (UAn1BRT) ........................................................................................... 11-30
11.2.12 UARTn0 Baud Rate Adjustment Register (UAn0BRC) ........................................................................ 11-31
11.2.13 UARTn1 Baud Rate Adjustment Register (UAn1BRC) ........................................................................ 11-31
11.2.14 UARTn0 Status Register (UAn0STAT) ................................................................................................ 11-32
11.2.15 UARTn1 Status Register (UAn1STAT) ................................................................................................ 11-34
11.3 Description of Operation ......................................................................................................................... 11-36
11.3.1 Synchronous Serial Port (SSIO) .............................................................................................................. 11-36
11.3.2 Asynchronous Serial Interface (UART) .................................................................................................. 11-45
Chapter 12
12. I2C Bus Unit ................................................................................................................................................. 12-1
12.1 General Description ................................................................................................................................... 12-1
12.1.1 Features ...................................................................................................................................................... 12-1
12.1.2 Configuration ............................................................................................................................................. 12-2
12.1.3 List of Pins ................................................................................................................................................. 12-3
12.1.4 Pin Setting .................................................................................................................................................. 12-3
12.2 Description of Registers ............................................................................................................................. 12-4
12.2.1 List of Registers ......................................................................................................................................... 12-4
12.2.2 I2C Bus Unit 0 Mode Register (I2U0MSS) ............................................................................................... 12-5
12.2.3 I2C Bus 0 Receive Register (Master) (I2UM0RD).................................................................................... 12-6
12.2.4 I2C Bus 0 Slave Address Register (Master) (I2UM0SA) .......................................................................... 12-7
12.2.5 I2C Bus 0 Transmit Data Register (Master) (I2UM0TD) .......................................................................... 12-8
12.2.6 I2C Bus 0 Control Register (Master) (I2UM0CON) ................................................................................. 12-9
12.2.7 I2C Bus 0 Mode Register (Master) (I2UM0MOD) ................................................................................. 12-10
12.2.8 I2C Bus 0 Status Register (Master) (I2UM0STR) ................................................................................... 12-12
12.2.9 I2C Bus 0 Receive Register (Slave) (I2US0RD) ..................................................................................... 12-14
12.2.10 I2C Bus 0 Slave Address Register (Slave) (I2US0SA).......................................................................... 12-15
12.2.11 I2C Bus 0 Transmit Data Register (Slave) (I2US0TD) ......................................................................... 12-16
12.2.12 I2C Bus 0 Control Register (Slave) (I2US0CON) ................................................................................. 12-17
12.2.13 I2C Bus 0 Mode Register (Slave) (I2US0MD) ...................................................................................... 12-18
FEUL62Q1000
ML62Q1000 Series User's Manual
Contents-5
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