LAPIS Semiconductor ML62Q1000 Series User Manual page 344

Bit symbol
Bit no.
name
3 FTnSPC
2 FTnSP
1 FTｎSTC
0 FTnST
[Note]
Ÿ
The pulse input to the EXTRG0 to EXTRG7 pin must have "the noise removal width chosen by FTnTRF2
to 0 bits of FTnTRG1 register + two timer clocks" or longer.
FEUL62Q1000
This bit is used to choose whether to enable clearing the counter when a trigger event for
counter-stop occurs (only when the edge is chosen by the FTnTRM1-0 bits).
The setting of this bit is valid regardless of the setting of the FTnSP bit.
If an update request of FTnP, FTnEA, FTnEB and FTnDT by the FTCUDn bit of FTCUD
register is generated when the trigger event occurs, the FTnP, FTnEA, FTnEB and FTnDT
register gets updated at the same time as the counter clear.
However, the counter is not cleared at emergency stop regardless the data of this bit.
0: The counter clear is disabled (Initial value)
1: The counter clear is enabled
This bit is used to choose whether to enable stopping the counter by a trigger event.
0: The counter stop is disabled (Initial value)
1: The counter stop is enabled
This bit is used to choose whether to enable clearing the counter when a trigger event for
counter-start occurs (only when the edge is chosen by the FTnTRM1-0 bits).
The setting of this bit is valid regardless of the setting of the FTnST bit.
If an update request of FTnP, FTnEA, FTnEB and FTnDT by the FTCUDn bit of FTCUD
register is generated when the trigger event occurs, the FTnP, FTnEA, FTnEB and FTnDT
register gets updated at the same time as the counter clear.
However, the counter is not cleared at emergency stop regardless the data of this bit.
0: The counter clear is disabled (Initial value)
1: The counter clear is enabled
This bit is used to choose whether to enable starting the counter by a trigger event.
0: The counter start is disabled (Initial value)
1: The counter start is enabled
ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
Description
9-24