Low Speed Time Base Counter Register (Ltbr) - LAPIS Semiconductor ML62Q1000 Series User Manual

7.2.2 Low Speed Time Base Counter Register (LTBR)

The low speed time base counter register (LTBR) is a specific function register (SFR) to read the value of the time base
counter.
If the write-operation is performed onto the LTBR, the all bits T128HZ to T1Hz are initialized to "0".
LTBR is also initialized to "0x00" at the system reset.
Address: 0xF060 (LTBR)
Access: R/W
Access size: 8 bit
Initial value: 0x00
15 14
Word
Byte
- -
Bit
R/W R R
Initial 0 0
value
[Note]
Ÿ
A time base counter interrupt may occur depending on a write timing to the LTBR. See the program
example for initializing described in Section 7.3.1 "Operation of the Low-speed Time Base Counter".
Ÿ
T128HZ to T1HZ signals have "0" level in the first half cycle and "1" level in the last half. For example,
T1HZ signal gets reset to "0" by writing any data to LTBR and it get to "1" about 0.5sec later and returns
to "1" about 1sec later from the reset. The low-speed time base counter interrupt occurs at the falling
edge ("1" to "0") of the signal. See "Time base counter interrupt timing and reset timing of reset by
writing to LTBR" for details about the waveform of signal. See Figure 7-5 "Low speed time base counter
interrupt timing and reset timing of reset by writing to LTBR" for details of the T128Hz to T1Hz waveform.
Ÿ
When the high-speed clock is used for the system clock, read the LTBR register twice to verify the data
to prevent reading uncertain data while counting-up.
FEUL62Q1000
13 12 11 10
-
- - - -
R R R R
0 0 0 0
Chapter 7 Low Speed Time Base Counter
9 8 7 6
-
- -
T1HZ T2HZ T4HZ T8HZ
R R R/W R/W
0 0 0 0
ML62Q1000 Series User's Manual
5 4 3 2
LTBR
T16H T32H
Z Z
R/W R/W R/W R/W
0 0 0 0
1 0
T64H T128
Z HZ
R/W R/W
0 0
7-7