LAPIS Semiconductor ML62Q1000 Series User Manual page 669

22.3.1.2 Interrupt Output
Figure 22-5 shows an example of the operation timing chart when the VLS0 interrupt output without sampling is
specified.
VLS0EN bit
Threshold voltage (at rise)
(at fall)
VLS0 comparator
comparison result
VLS0 interrupt
Figure 22-5 Operation Timing Diagram When the VLS0 Interrupt Output without Sampling is specified
The operation shown in Figure 22-5 is described below:
(1) Choose a detection voltage by the VLS0LV3 to VLS0LV0 bits of the VLS0LV register.
(2) Choose "without sampling" by the VLS0SM1 and VLS0SM0 bits of the VLS0SMP register.
(3) Write "0x02" or "0x03" to VLS0AMD[1:0] bits of VLS0MOD register in order to choose the supervisor mode.
(4) Choose an operation function by the VLS0SEL1 and VLS0SEL0 bits of the VLS0MOD register.
(5) Write "1" to the VLS0EN bit to enable VLS0 operation.
(6) When the comparison result of the VLS0 comparator is stabilized, the VLS0RF bit is set to "1".
(7) When V becomes below the threshold voltage (V
DD
(8) If V becomes equal to or above the threshold voltage (V
DD
VLS0 interrupt.
(9) Write "0" to the VLS0EN bit to disable VLS0 operation.
FEUL62Q1000
(1)~(5)
↓
VLS0RF
V
DD
Stabilization
time
VLS0F
(6) (7)
↓ ↓
, the VLS0F bit is set to "1" to generate the VLS0 interrupt.
VLSF)
), the VLS0F bit is cleared to "0" to generate the
VLSR
ML62Q1000 Series User's Manual
Chapter 22 Voltage Level Supervisor
(8) (9)
↓ ↓
V
VLSR
V
VLSF
V
SS
22-14