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ML610Q174
LAPIS Semiconductor ML610Q174 Manuals
Manuals and User Guides for LAPIS Semiconductor ML610Q174. We have
2
LAPIS Semiconductor ML610Q174 manuals available for free PDF download: User Manual
LAPIS Semiconductor ML610Q174 User Manual (507 pages)
Brand:
LAPIS Semiconductor
| Category:
Microcontrollers
| Size: 2.93 MB
Table of Contents
Feul610Q174
2
Feul610Q174
3
Feul610Q174
4
Table of Contents
5
Chapter 1 Overview
17
Features
18
Feul610Q174
20
Configuration of Functional Blocks
21
Block Diagram of ML610Q174
21
Pins
22
Pin Layout
22
Pin Layout of ML610Q174 QFP Package
22
List of Pins
23
Feul610Q174
24
Feul610Q174
25
Pin Description
26
Termination of Unused Pins
30
Chapter 2 CPU and Memory Space
31
Overview
32
Program Memory Space
32
Data Memory Space
33
Instruction Length
34
Data Type
34
Description of Registers
35
List of Registers
35
Data Segment Register (DSR)
36
Chapter 3 Reset Function
37
Overview
38
Features
38
Configuration
38
List of Pin
38
Description of Registers
39
List of Registers
39
Reset Status Register (RSTAT)
39
Description of Operation
40
Operation of System Reset Mode
40
Chapter 4 MCU Control Function
41
Overview
42
Features
42
Configuration
42
Description of Registers
43
List of Registers
43
Stop Code Acceptor (STPACP)
44
Standby Control Register (SBYCON)
45
Block Control Register 0 (BLKCON0)
46
Block Control Register 2 (BLKCON2)
47
Block Control Register 4 (BLKCON4)
49
Block Control Register 6 (BLKCON6)
50
Block Control Register 7 (BLKCON7)
51
Description of Operation
52
Program Run Mode
52
HALT Mode
52
STOP Mode
53
STOP Mode When CPU Operates with Low-Speed Clock
53
STOP Mode When CPU Operates with High-Speed Clock
53
Note on Return Operation from STOP/HALT Mode
55
Block Control Function
56
Chapter 5 Interrupts (Ints)
57
Overview
58
Features
58
Description of Registers
59
List of Registers
59
Interrupt Enable Register 0 (IE0)
60
Interrupt Enable Register 1 (IE1)
61
Interrupt Enable Register 2 (IE2)
62
Interrupt Enable Register 3 (IE3)
63
Interrupt Enable Register 4 (IE4)
64
Interrupt Enable Register 5 (IE5)
65
Interrupt Enable Register 6 (IE6)
66
Interrupt Enable Register 7 (IE7)
67
Interrupt Request Register 0 (IRQ0)
68
Interrupt Request Register 1 (IRQ1)
69
Interrupt Request Register 2 (IRQ2)
70
Interrupt Request Register 3 (IRQ3)
71
Interrupt Request Register 4 (IRQ4)
72
Interrupt Request Register 5 (IRQ5)
73
Interrupt Request Register 6 (IRQ6)
74
Interrupt Request Register 7 (IRQ7)
76
Description of Operation
77
Maskable Interrupt Processing
78
Non-Maskable Interrupt Processing
78
Software Interrupt Processing
78
Notes on Interrupt Routine
79
Interrupt Disable State
82
Chapter 6 Clock Generation Circuit
83
Overview
84
Features
84
Configuration
84
List of Pins
85
Clock Configuration
85
Description of Registers
86
List of Registers
86
Frequency Control Register 0(FCON0)
87
Frequency Control Register 1 (FCON1)
89
Frequency Status Register (FSTAT)
90
Description of Operation
91
Low-Speed Clock
91
Low-Speed Clock Generation Circuit (32.768 Crystal Oscillation Circuit)
91
Low-Speed Clock Generation Circuit (Built-In RC Oscillating Circuit)
91
Operation of the Low-Speed Clock Generation Circuit
92
High-Speed Clock
93
Built-In PLL Oscillation Mode
93
Crystal/Ceramic Oscillation Mode
93
High-Speed External Clock Input Mode
94
Operation of High-Speed Clock Generation Circuit
95
Switching of System Clock
97
Register Setup of the Port
98
When the P21 Pin (Outclk:output) Operates as the High-Speed Clock Output Function
98
When the P20 Pin (Lsclk:output) Operates as the Low-Speed Clock Output Function
99
When the P36 Pin (Lsclk:output) Operates as the Low-Speed Clock Output Function
100
Chapter 7 Time Base Counter
101
Overview
102
Features
102
Configuration
102
Description of Registers
104
List of Registers
104
Low-Speed Time Base Counter (LTBR)
105
High-Speed Time Base Counter Divide Register (HTBDR)
106
Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH)
107
Description of Operation
108
Low-Speed Time Base Counter
108
High-Speed Time Base Counter
109
Low-Speed Time Base Counter Frequency Adjustment Function
110
Chapter 8 Timers
111
Overview
112
Features
112
Configuration
112
Description of Registers
114
List of Registers
114
Timer 0 Data Register (TM0D)
115
Timer 1 Data Register (TM1D)
116
Timer 8 Data Register (TM8D)
117
Timer 9 Data Register (TM9D)
118
Timer a Data Register (TMAD)
119
Timer B Data Register (TMBD)
120
Timer 0 Counter Register (TM0C)
121
Timer 1 Counter Register (TM1C)
122
Timer 8 Counter Register (TM8C)
123
Timer 9 Counter Register (TM9C)
124
Timer a Counter Register (TMAC)
125
Timer B Counter Register (TMBC)
126
Timer 0 Control Register 0 (TM0CON0)
127
Timer 1 Control Register 0 (TM1CON0)
128
Timer 8 Control Register 0 (TM8CON0)
129
Timer 9 Control Register 0 (TM9CON0)
130
Timer a Control Register 0 (TMACON0)
131
Timer B Control Register 0 (TMBCON0)
132
Timer 0 Control Register 1 (TM0CON1)
133
Timer 1 Control Register 1 (TM1CON1)
134
Timer 8 Control Register 1 (TM8CON1)
135
Timer 9 Control Register 1 (TM9CON1)
136
Timer a Control Register 1 (TMACON1)
137
Timer B Control Register 1 (TMBCON1)
138
Description of Operation
139
Chapter 9 Watchdog Timer
141
Overview
142
Features
142
Configuration
142
Description of Registers
143
List of Registers
143
Watchdog Timer Control Register (WDTCON)
144
Watchdog Timer Mode Register (WDTMOD)
145
Description of Operation
146
Handling Example When You Do Not Want to Use the Watch Dog Timer
148
Chapter 10 PWM
149
Overview
150
Features
150
Configuration
151
List of Pins
153
Description of Registers
153
List of Registers
153
PWM4 Period Registers (PW4PL, PW4PH)
154
PWM4 Duty Registers (PW4DL, PW4DH)
155
PWM4 Counter Registers (PW4CH, PW4CL)
156
PWM4 Control Register 0 (PW4CON0)
157
PWM4 Control Register 1 (PW4CON1)
159
PWM4 Control Register 2 (PW4CON2)
160
PWM4 Control Register 3 (PW4CON3)
162
PWM5 Period Registers (PW5PL, PW5PH)
163
PWM5 Duty Registers (PW5DL, PW5DH)
164
PWM5 Counter Registers (PW5CH, PW5CL)
165
PWM5 Control Register 0 (PW5CON0)
166
PWM5 Control Register 1 (PW5CON1)
168
PWM5 Control Register 2 (PW5CON2)
169
PWM6 Period Registers (PW6PL, PW6PH)
171
PWM6 Duty Registers (PW6DL, PW6DH)
172
PWM6 Counter Registers (PW6CH, PW6CL)
173
PWM6 Control Register 0 (PW6CON0)
174
PWM6 Control Register 1 (PW6CON1)
176
PWM6 Control Register 2 (PW6CON2)
177
Description of Operation
179
Repeat Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Not Used) (P45MD="1", P4DTMD="0", P4MD="0")
185
One-Shot Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Not Used) (P45MD="1", P4DTMD="0", P4MD="1")
188
Repeat Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Used) (P45MD="1", P4DTMD="1", P4MD="0")
191
One-Shot Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Used) (P45MD="1", P4DTMD="1", P4MD="1")
195
Software Start Mode
199
Software Start or External Input Start Mode
199
External Input Start Mode
202
Software Start or External Input Clear Mode
204
Emergency Stop Operation
207
Specifying Port Registers
209
Functioning P34 Pin (PWM4) as PWM Output
209
Functioning P43 Pin (PWM4) as PWM Output
210
Functioning P35 Pin (PWM5) as PWM Output
211
Functioning P47 Pin (PWM5) as PWM Output
212
Functioning P53 Pin (PWM6) as PWM Output
213
Chapter 11 Synchronous Serial Port
214
Overview
215
Features
215
Configuration
215
List of Pins
217
Description of Registers
218
List of Registers
218
Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH)
219
Serial Port Transmit/Receive Buffers (SIO1BUFL, SIO1BUFH)
220
Serial Port Control Register (SIO0CON)
221
Serial Port Control Register (SIO1CON)
222
Serial Port Mode Register 0 (SIO0MOD0)
223
Serial Port Mode Register 0 (SIO1MOD0)
224
Serial Port Mode Register 1 (SIO0MOD1)
225
Serial Port Mode Register 1 (SIO1MOD1)
226
Description of Operation
227
Transmit Operation
227
Receive Operation
228
Transmit/Receive Operation
229
Register Setup of the Port
230
When Operating the SSIO Function in Master Mode Using P42 Pin (Sout0:Output), P41 Pin
230
(Sck0:Input/Output), and P40 Pin (Sin0:Input)
230
When Operating the SSIO Function in Slave Mode Using P42 Pin (Sout0:Output), P41 Pin (Sck0:Input/Output), and P40 Pin (Sin0:Input)
230
When Operating the SSIO Function in Master Mode Using P52 Pin (Sout1:Output), P51 Pin (Sck1:Input/Output), and P50 Pin (Sin1:Input)
230
When Operating the SSIO1 Function in Slave Mode Using P52 Pin (Sout1:Output), P51 Pin
230
(Sck1:Input/Output), and P50 Pin (Sin1:Input)
230
Chapter 12 UART
234
Overview
235
Features
235
Configuration
235
List of Pins
236
Description of Registers
236
List of Registers
236
UART0 Transmit/Receive Buffer (UA0BUF)
237
UART1 Transmit/Receive Buffer (UA1BUF)
237
UART0 Control Register (UA0CON)
238
UART1 Control Register (UA1CON)
238
UART0 Mode Register 0 (UA0MOD0)
239
UART1 Mode Register 0 (UA1MOD0)
240
UART0 Mode Register 1 (UA0MOD1)
241
UART1 Mode Register 1 (UA1MOD1)
243
UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH)
245
UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH)
246
UART0 Status Register (UA0STAT)
247
UART1 Status Register (UA1STAT)
249
Description of Operation
251
Transfer Data Format
251
Baud Rate
252
Transmit Data Direction
253
Transmit Operation
254
Receive Operation
256
Detection of Start Bit
258
Sampling Timing
258
Reception Margin
259
Register Setup of the Port
260
When Operating the UART Function Using PF3 Pin (Txd0:Output) and PF2 Pin (Rxd0:Input)
270
When Operating the UART Function Using PF7 Pin (Txd1:Output) and PF6 Pin (Rxd1:Input)
271
Chapter 13 I 2 C Bus Interface
272
Overview
273
Features
273
Configuration
273
List of Pins
273
I2C Bu Interface
273
Description of Registers
274
List of Registers
274
I 2 C Bus 0 Receive Register (I2C0RD)
275
I 2 C Bus 0 Slave Address Register (I2C0SA)
276
I 2 C Bus 0 Transmit Data Register (I2C0TD)
277
I 2 C Bus 0 Control Register (I2C0CON)
278
I 2 C Bus 0 Mode Register (I2C0MOD)
279
I 2 C Bus 0 Status Register (I2C0STAT)
280
Description of Operation
281
Communication Operating Mode
281
Start Condition
281
Slave Address Transmit Mode
281
Data Transmit Mode
281
Data Receive Mode
281
Control Register Setting Wait State
281
Stop Condition
281
Communication Operation Timing
282
Operation Waveforms
284
Functioning P41(SCL) and P40(SDA) as the I2C
285
Chapter 14 Port 0
286
Overview
287
Features
287
Configuration
287
List of Pins
288
Port 0 Data Register (P0D)
290
Port 0 Control Registers 0, 1 (P0CON0, P0CON1)
291
External Interrupt Control Registers 0, 1 (EXICON0, EXICON1)
292
External Interrupt Control Register 2 (EXICON2)
293
Description of Operation
294
External Interrupt
294
Interrupt Request
294
Chapter 15 Port 1
296
Overview
297
Features
297
Configuration
297
List of Pins
297
Description of Registers
298
List of Registers
298
Port 1 Data Register (P1D)
299
Port 1 Control Registers 0,1 (P1CON0, P1CON1)
300
Description of Operation
301
Input Port Function
301
Chapter 16 Port 2
302
Overview
303
Features
303
Configuration
303
List of Pins
303
Description of Registers
304
List of Registers
304
Port 2 Data Register (P2D)
305
Port 2 Control Registers 0, 1 (P2CON0, P2CON1)
306
Port 2 Mode Register (P2MOD)
307
Description of Operation
309
Output Port Function
309
Secondary Function
309
Chapter 17 Port 3
310
Overview
311
Features
311
Configuration
311
List of Pins
312
Description of Registers
313
List of Registers
313
Port 3 Data Register (P3D)
314
Port 3 Direction Register (P3DIR)
315
Port 3 Control Registers 0, 1 (P3CON0, P3CON1)
316
Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1)
318
Description of Operation
320
Input/Output Port Functions
320
Secondary Function
320
Chapter 18 Overview
322
Features
322
Configuration
322
List of Pins
323
Description of Registers
324
List of Registers
324
Port 4 Data Register (P4D)
325
Port 4 Direction Register (P4DIR)
326
Port 4 Control Registers 0, 1 (P4CON0, P4CON1)
327
Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1)
329
Description of Operation
332
Input/Output Port Functions
332
Chapter 19 Port 5
334
Overview
334
Features
334
Configuration
334
List of Pins
335
Description of Registers
336
List of Registers
336
Port 5 Data Register (P5D)
337
Port 5 Direction Register (P5DIR)
338
Port 5 Control Registers 0, 1 (P5CON0, P5CON1)
339
Port 5 Mode Registers 0, 1 (P5MOD0, P5MOD1)
341
Description of Operation
343
Input/Output Port Functions
343
Chapter 20 Overview
345
Features
345
Configuration
345
List of Pins
346
Description of Registers
347
List of Registers
347
Chapter 21 Port 9
353
Overview
354
Features
354
Configuration
354
List of Pins
354
Description of Registers
355
List of Registers
355
Port 9 Data Register (P9D)
356
Port 9 Control Registers 0, 1 (P9CON0, P9CON1)
357
Description of Operation
358
Output Port Functions
358
Chapter 22 Port C
359
Overview
360
Features
360
Configuration
360
List of Pins
361
Description of Registers
362
List of Registers
362
Port C Data Register (PCD)
363
Port C Direction Register (PCDIR)
364
Port C Control Registers 0, 1 (PCCON0, PCCON1)
365
Description of Operation
367
Input/Output Port Functions
367
Chapter 23 Port D
368
Overview
369
Features
369
Configuration
369
List of Pins
370
Description of Registers
371
List of Registers
371
Port D Data Register (PDD)
372
Port D Direction Register (PDDIR)
373
Port D Control Registers 0, 1 (PDCON0, PDCON1)
374
Description of Operation
376
Input/Output Port Functions
376
Chapter 24 Port F
377
Overview
378
Features
378
Configuration
378
List of Pins
379
Description of Registers
380
Port F Mode Registers 0, 1 (PFMOD0, PFMOD1)
385
Description of Operation
387
Input/Output Port Functions
387
Secondary, Tertiary and Fourthly Functions
387
Chapter 25 LCD Drivers
388
Overview
389
Features
390
Configuration of the LCD Drivers
390
Configuration of the LCD Drive Voltage Control Circuit
391
List of Pins
392
Bias Circuit Control Register 0 (BIASCON)
394
Display Mode Register 0 (DSPMOD0)
395
Display Control Register (DSPCON)
396
Bias Circuit Mode Register 0 (BIASMOD)
397
Display Registers (DSPR00 to DSPR17, DSPR20 to DSPR27)
398
LCD Port Segment Selection Register 1 (LSELS1)
400
LCD Port Segment Selection Register 2 (LSELS2)
402
LCD Port Segment Selection Register 4 (LSELS4)
404
LCD Port Common Selection Register 0 (LSELC0)
406
Description of Operation
407
Operation of LCD Drivers and Bias Generation Circuit
407
Display Register Segment Map
408
Built-In Division Resistance for LCD Drive Voltage Generation
409
Common Output Waveforms for 1/4 Duty and 1/3 Bias
410
Segment Output Waveform for 1/4 Duty and 1/3 Bias
411
Common Output Waveforms for 1/4 Duty and 1/2 Bias
412
Segment Output Waveform for 1/4 Duty and 1/2 Bias
413
Chapter 26 Successive Approximation Type A/D Converter (SA-ADC)
414
Overview
415
Configuration
415
List of Pins
416
Description of Registers
417
List of Registers
417
SA-ADC Result Register 0L (SADR0L)
418
SA-ADC Result Register 0H (SADR0H)
418
SA-ADC Result Register 1L (SADR1L)
419
SA-ADC Result Register 1H (SADR1H)
419
SA-ADC Result Register 2L (SADR2L)
420
SA-ADC Result Register 2H (SADR2H)
420
SA-ADC Result Register 3L (SADR3L)
421
SA-ADC Result Register 3H (SADR3H)
421
SA-ADC Result Register 4L (SADR4L)
422
SA-ADC Result Register 4H (SADR4H)
422
SA-ADC Result Register 5L (SADR5L)
423
SA-ADC Result Register 5H (SADR5H)
423
SA-ADC Result Register 6L (SADR6L)
424
SA-ADC Result Register 6H (SADR6H)
424
SA-ADC Result Register 7L (SADR7L)
425
SA-ADC Result Register 7H (SADR7H)
425
SA-ADC Result Register 8L (SADR8L)
426
SA-ADC Result Register 8H (SADR8H)
426
SA-ADC Result Register 9L (SADR9L)
427
SA-ADC Result Register 9H (SADR9H)
427
SA-ADC Result Register al (SADRAL)
428
SA-ADC Result Register AH (SADRAH)
428
SA-ADC Result Register BL (SADRBL)
429
SA-ADC Result Register BH (SADRBH)
429
SA-ADC Control Register 0 (SADCON0)
430
SA-ADC Control Register 1 (SADCON1)
431
SA-ADC Mode Register 0 (SADMOD0)
432
SA-ADC Mode Register 1 (SADMOD1)
434
Operation of Successive Approximation Type A/D Converter
436
Chapter 27 Battery Level Detector
437
Overview
438
Features
438
Configuration
438
Description of Registers
439
List of Registers
439
Battery Level Detector Control Register 0 (BLDCON0)
440
Battery Level Detector Control Register 1 (BLDCON1)
441
Description of Operation
442
Threshold Voltage
442
Operation of Battery Level Detector
443
Chapter 28 Analog Comparator
444
Overview
445
Features
445
Configuration
445
List of Pins
446
Description of Registers
446
List of Registers
446
Comparator0 Control Register 0 (CMP0CON0)
447
Comparator0 Control Registers 1 (CMP0CON1)
448
Comparator1 Control Register 0 (CMP1CON0)
449
Comparator0 Control Registers 1 (CMP1CON1)
450
Description of Operation
451
Analog Comparator Function
451
Interrupt Request
452
Chapter 29 Power Supply Circuit
453
Overview
454
Features
454
Configuration
454
List of Pins
454
Description of Operation
455
Chapter 30 Flash Memory Programming
456
Overview
457
Features
457
Description of Registers
458
List of Registers
458
Flash Address Register L,H (FLASHAL,H)
459
Flash Data Register L,H (FLASHDL,H)
461
Flash Control Register (FLASHCON)
462
Flash Acceptor (FLASHACP)
463
Flash Segment Register (FLASHSEG)
463
Flash Self Register (FLASHSLF)
464
Flash Remap Register (REMAPADD)
465
Description of Operation
466
Block Erase Function
468
Sector Erase Function
469
1-Word Write Function
470
Remap Function by Software
471
Remap Function by Hardware (External Terminal)
472
Notes in Use
473
Chapter 31 On-Chip Debug Function
474
Overview
475
How to Connect the On-Chip Debug Emulator
475
Chapter 32 Code-Option
476
Overview
477
Features
477
Description of Registers
478
List of Registers
478
Code-Option Register (CODEOP0)
479
The Method of a Setup of Code-Option Data
480
The Format of Code-Option Data
480
The Method of Programming of Code-Option Data
480
Appendixes
481
Appendix A Registers
482
Appendix B Package Dimensions: ML610Q174-Xxxgazwaal
490
Appendix C Electrical Characteristics
490
Appendix D the Example of an Application Circuit
502
Appendix E Check List
503
Revision History
506
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LAPIS Semiconductor ML610Q174 User Manual (17 pages)
Reference Board
Brand:
LAPIS Semiconductor
| Category:
Computer Hardware
| Size: 0.67 MB
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