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Figure 13-5 shows the operation timing and control method when an acknowledgment error occurs.
Figure 13-5 Operation suspend timing at occurrence of acknowledgment error
When the values of the transmitted bit and the I2CMn_SDA pin do not coincide, the I2MnER bit of the I
status register (I2MnSTAT) is set to "1" and the I2CMn_SDA pin output is disabled until termination of the subsequent
byte data communication.
Figure 13-6 shows the operation timing and control method when transmission fails.
FEUL62Q1000
Register
I2MnSA="xxxxxxx0B"
setting
I2MnCON="01H"
S A
I2CMn_SDA pin
I2MnINT
I2MnST bit
I2MnRD register
I2MnACR bit
I2MnSA="xxxxxxx0B"
Register
I2MnCON="01H"
setting
S A
I2CMn_SDA pin
I2MnINT
I2MnST bit
I2MnRD register
I2MnER bit
Figure 13-6 Operation timing when transmission fails
Acknowledge error
A
A
A
A
A
A
R
A
6
5
4
3
2
1
0
W
Values of I2MnSA
Transmission failure
A
A
A
A
6
5
4
3
ML62Q1000 Series User's Manual
Chapter 13 I2C Master
I2MnCON="02H"
P
Values of I2MnSA
I2MnCON="00H"
Undefined data
2
C master 0
13-18
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