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Bit No.
Bit symbol name
2 to 0
clmod2 to clmod0
The following table shows values to be set to CR8 register for execution of each operation mode.
Multiplication 16 bit x 16 bit (initial value)
Division 32 bit/16 bit
Division 32 bit/32 bit
Multiply-accumulate (non-saturating) 16 bit
x 16 bit + 32 bit
Multiply-accumulate (saturating)
16 bit x 16 bit + 32 bit
The following table shows flags changing during each operation.
Operation mode
Multiplication
16 bit x 16 bit
Division
32 bit/16 bit
Division
32 bit/32 bit
Multiply-accumulate
(non-saturating)
16 bit x 16 bit + 32 bit
Multiply-accumulate
(saturating)
16 bit x 16 bit + 32 bit
●: Varies depending on the result. -: Retains the previous value.
FEUL62Q1000
Bits to choose the operation mode.
000:
Multiplication 16 bit x 16 bit (initial value)
001:
Division 32 bit/16 bit
010:
Multiply-accumulate (non-saturating) 16 bit x 16 bit + 32 bit
011:
Multiply-accumulate (saturating) 16 bit x 16 bit + 32 bit
100:
No operation function
101:
Division 32 bit/32 bit
110:
No operation function
111:
No operation function
Value set to CR8
sign
1 (signed)
0 (unsigned)
1 (signed)
0 (unsigned)
1 (signed)
0 (unsigned)
1 (signed)
0 (unsigned)
1 (signed)
0 (unsigned)
ML62Q1000 Series User's Manual
Chapter 2 CPU and Memory Space
Description
Signed
0x90
0x91
0x95
0x92
0x93
c
z
s
●
●
-
●
-
-
●
●
●
●
●
-
●
●
●
●
●
-
●
●
●
●
●
●
●
●
●
●
●
●
Unsigned
0x80
0x81
0x85
0x82
0x83
ov
q
-
-
-
-
●
-
-
-
●
-
-
-
●
-
●
-
●
●
●
●
2-10
- Quick Links:
- Block Diagram of Ml62Q1300 Group
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