LAPIS Semiconductor ML62Q1000 Series User Manual page 343

Bit symbol
Bit no.
name
12 to 8 FTnSTSS,
FTnSTS3 to
FTnSTS0
6 FTnDCLH
5 FTnCST
4 -
FEUL62Q1000
These bits are used to choose the trigger event source of FTMn. Choose a source except for
the interrupt target (e.g. do not choose the FTM0TRG when using the functional timer FTM0).
Ÿ TIMER, CAPTURE, PWM1, PWM2 mode
00000: External Trigger 0 Input (EXTRG0)
00001: External Trigger 1 Input (EXTRG1)
00010: External Trigger 2 Input (EXTRG2)
00011: External Trigger 3 Input (EXTRG3)
00100: External Trigger 4 Input (EXTRG4)
00101: External Trigger 5 Input (EXTRG5)
00110: External Trigger 6 Input (EXTRG6)
00111: External Trigger 7 Input (EXTRG7)
01000: Comparator 0 Output (COMP0D)
010X1: Reserved
01100: For the clock mutual monitoring in the safety function
011X1: Reserved
X: Don't care "0" or "1"
Ÿ TIMER, PWM1, PWM2 mode
10000: 16-bit Timer 0 Trigger (TMH0TRG)
10001: 16-bit Timer 1 Trigger (TMH1TRG)
10010: 16-bit Timer 2 Trigger (TMH2TRG)
10011: 16-bit Timer 3 Trigger (TMH3TRG)
10100: 16-bit Timer 4 Trigger (TMH4TRG)
10101: 16-bit Timer 5 Trigger (TMH5TRG)
10110: 16-bit Timer 6 Trigger (TMH6TRG)
10111: 16-bit Timer 7 Trigger (TMH7TRG)
11000: Functional Timer 0 Trigger (FTM0TRG)
11001: Functional Timer 1 Trigger (FTM1TRG)
11010: Functional Timer 2 Trigger (FTM2TRG)
11011: Functional Timer 3 Trigger (FTM3TRG)
11100: Functional Timer 4 Trigger (FTM4TRG)
11101: Functional Timer 5 Trigger (FTM5TRG)
11110: Functional Timer 6 Trigger (FTM6TRG)
11111: Functional Timer 7 Trigger (FTM7TRG)
This bit is used to disable the counter clear by a trigger event when the positive phase output
is "H" level.
Ÿ TIMER, PWM1, PWM2 mode
0: The counter clear is enabled regardless the positive phase output (initial value)
1: The counter clear is disabled when the positive phase output is "H" level.
Ÿ CAPTURE mode
This bit is invalid
This bit is used to choose the operation mode for starting the count by a trigger event.
0: A trigger event always can start the counter when the counter stops (except for
emergency stop) (initial value)
1: A trigger event does not start the counter until reading FTnC register when the counter
stops (except for emergency stop)
Reserved bit
ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
Description
(Initial value)
9-23