LAPIS Semiconductor ML62Q1000 Series User Manual page 422

SSIO mode
SUnMOD
SUnMD1
0
UART mode
SUnMOD
SUnMD1
1
1
[Note]
Ÿ
Set "0x00" to the SUnDLYL register in the SSIO slave mode.
Ÿ
The SUnDLYL register is invalid in the SSIO master reception mode.
FEUL62Q1000
SUnMD0 SnCK4 SnCK3
0 0
0/1
1 0
UAnMOD
SUnMD0 UnCK1
0
0
1
0
1
1
Chapter 11 Serial Communication Unit
SIOnMOD
SnCK2 SnCK1
0 0
0/1 0/1
Base clock
LSCLK
HSCLK
LSCLK
HSCLK
ML62Q1000 Series User's Manual
Base clock
LSCLK (Initial value)
HSCLK
11-20