LAPIS Semiconductor ML62Q1000 Series User Manual page 506

13.3.1.5 Control Register Setting Wait State
Control register setting wait state start
Generate I
Confirm I
Load received data into CPU
Writes data transmitted next time
Set communication mode
Set I
Control register setting wait state
transmission/reception mode, stop
condition, or restart condition)
13.3.1.6 Data Transmission Mode
Data transmit mode start
Transmit value of I
Acknowledgment signal is received by
Data transmit mode completed
FEUL62Q1000
2
C bus master 0 interrupt
2
C master 0 status register
2
C master 0 control register
completed
(move to one of: data
2
C master 0
transmit data register
2
I C
(move to control register
setting wait state)
ML62Q1000 Series User's Manual
When entering the control register setting wait state,
an interrupt (I2CMnINT) is generated by hardware
Confirm the following bits of the I2MnSTAT register:
I2MnER bit: Transmit error flag
I2MnACR bit: Acknowledgment data
<Only when data is received> Read the I2MnRD register
and load received data into the CPU
I2MnR7 to I2MnR0 bits: 8-bit receive data
<Only when data is transmitted> Set the I2MnTD register
Write data to be transmitted next time
I2MnT7 to I2MnT0 bits: 8-bit transmit data
<Only when operation mode is changed> Set the I2MnMOD
register
Set communication mode through each bit
Set I2MnCON register
I2MnST bit: Starting communication (I2MnST=1)
I2MnSP bit: Stop condition request (I2MnSP=1)
I2MnRS bit: Restart request (I2MnRS=1)
Transmission data that has been written to the I2MnTD register
is transmitted from I2CMn_SDA pin in MSB first
I2MnT7 to I2MnT0 bits: 8-bit transmitted data
Value transmitted from the I2CMn_SDA pin
is stored in the I2MnRD register
Acknowledgment signal is received by I2MnSTAT register
through hardware
I2MnACR bit: Acknowledgment data
2
I C master 0 control register (I2MnCON) setting wait state
Chapter 13 I2C Master
13-15