LAPIS Semiconductor ML62Q1000 Series User Manual page 853

Load/Store instructions
Instruction
ERn
L
Rn
XRn
QRn
ST ERn
Rn
XRn
QRn
(*1) When the immediately preceding instruction is for reading the data memory or not (not the instruction for reading the data
memory / the instruction for reading the data memory)
FEUL62Q1000
Min. execution cycle
No wait
mode
[EA] 1
[EA+] 1
[ERm] 1
Disp16[ERm] 2
Disp6[BP]
2
Disp6[FP] 2
Dadr 2
[EA] 1
[EA+] 1
[ERm] 1
Disp16[ERm] 2
Disp6[BP] 2
Disp6[FP] 2
Dadr 2
[EA] 2
[EA+] 2
[EA] 4
[EA+] 4
[EA] 1
[EA+] 1
[ERm] 1
Disp16[ERm] 2
Disp6[BP]
2
Disp6[FP] 2
Dadr 2
[EA] 1
[EA+] 1
[ERm] 1
Disp16[ERm] 2
Disp6[BP]
2
Disp6[FP] 2
Dadr 2
[EA] 2
[EA+] 2
[EA] 4
[EA+] 4
ROM reference cycle
No wait
Wait mode
mode
1 1
1 1
1 / 2 1
(*1)
2 1
2 1
2 1
2 1
1 1
1 1
1 / 2 1
(*1)
2 1
2 1
2 1
2 1
2 2
2 2
4 4
4 4
1 -
1 -
1 / 2 -
(*1)
2 -
2 -
2 -
2 -
1 -
1 -
1 / 2 -
(*1)
2 -
2 -
2 -
2 -
2 -
2 -
4 -
4 -
ML62Q1000 Series User's Manual
Appendix C Instruction Execution Cycle
Effect of
DSR
Wait mode
access
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
10 1
10 1
15 1
15 1
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
Effect of
[EA+]
addressing
-
-
1
1
1
1
1
-
-
1
1
1
1
1
-
-
-
-
-
-
1
1
1
1
1
-
-
1
1
1
1
1
-
-
-
-
C-3