LAPIS Semiconductor ML62Q1000 Series User Manual page 482

Figure 12-5 shows the operation timing and control method when an acknowledgment error occurs.
I2UM0RD register
Figure 12-5 Operation suspend timing at occurrence of acknowledgment error in the master mode
When the values of the transmitted bit and the I2CU0_SDA pin do not coincide, the I2UM0ER bit of the I
register (I2UM0STA) is set to "1" and the I2CU0_SDA pin output is disabled until termination of the subsequent byte
data communication.
Figure 12-6 shows the operation timing and control method when transmission fails.
I2UM0RD register
FEUL62Q1000
Register
I2UM0SA="xxxxxxx0B"
setting
I2UM0CON="01H"
S A
I2CU0_SDA pin
6
I2CU0INT
I2UM0ST bit
I2UM0ACR bit
I2UM0SA="xxxxxxx0B"
Register
I2UM0CON="01H"
setting
Transmission failure
S A
I2CU0_SDA pin
6
I2CU0INT
I2UM0ST bit
I2UM0ER bit
Figure 12-6 Operation timing when transmission fails in the master mode
Acknowledge error
I2UM0CON="02H"
A A A A A A R
A
W
5 4 3 2 1 0
Values of I2UM0SA
Values of I2UM0SA
I2UM0CON="00H"
A A A
A
5 4 3
ML62Q1000 Series User's Manual
Chapter 12 I2C Bus Unit
P
Undefined data
2
C bus 0 status
12-26