LAPIS Semiconductor ML62Q1000 Series User Manual page 7

Chapter 4
4. Power Management ........................................................................................................................................ 4-1
4.1 General Description ....................................................................................................................................... 4-1
4.1.1 Features .......................................................................................................................................................... 4-2
4.1.2 Configuration ................................................................................................................................................. 4-3
4.2 Description of Registers................................................................................................................................. 4-4
4.2.1 List of Registers ............................................................................................................................................. 4-4
4.2.2 Stop Code Acceptor (STPACP) ..................................................................................................................... 4-5
4.2.3 Standby Control Register (SBYCON) ........................................................................................................... 4-6
4.2.4 Software Reset Acceptor (SOFTRACP) ........................................................................................................ 4-7
4.2.5 Software Reset Control Register (SOFTRCON) ........................................................................................... 4-8
4.2.6 Block Clock Control Register 0 (BCKCON0) ............................................................................................... 4-9
4.2.7 Block Clock Control Register 1 (BCKCON1) ............................................................................................. 4-10
4.2.8 Block Clock Control Register 2 (BCKCON2) ............................................................................................. 4-12
4.2.9 Block Clock Control Register 3 (BCKCON3) ............................................................................................. 4-14
4.2.10 Block Reset Control Register 0 (BRECON0) ............................................................................................ 4-15
4.2.11 Block Reset Control Register 1 (BRECON1) ............................................................................................ 4-16
4.2.12 Block Reset Control Register 2 (BRECON2) ............................................................................................ 4-18
4.2.13 Block Reset Control Register 3 (BRECON3) ............................................................................................ 4-20
4.3 Description of Operation ............................................................................................................................. 4-21
4.3.1 Program Run Mode ...................................................................................................................................... 4-21
4.3.2 HALT Mode ................................................................................................................................................ 4-21
4.3.3 HALT-H mode............................................................................................................................................. 4-22
4.3.4 STOP mode .................................................................................................................................................. 4-23
4.3.5 STOP-D Mode ............................................................................................................................................. 4-24
4.3.6 Note on Return Operation from the Standby Mode ..................................................................................... 4-25
4.3.7 Operation of Each Function in Standby Mode ............................................................................................. 4-26
4.3.8 Block Control Function ............................................................................................................................... 4-28
Chapter 5
5. Interrupts ......................................................................................................................................................... 5-1
5.1 General Description ....................................................................................................................................... 5-1
5.1.1 Features .......................................................................................................................................................... 5-1
5.2 Description of Registers................................................................................................................................. 5-2
5.2.1 List of Registers ............................................................................................................................................. 5-2
5.2.2 Interrupt Enable Register 01 (IE01) ............................................................................................................... 5-5
5.2.3 Interrupt Enable Register 23 (IE23) ............................................................................................................... 5-6
5.2.4 Interrupt Enable Register 45 (IE45) ............................................................................................................... 5-8
5.2.5 Interrupt Enable Register 67 (IE67) ............................................................................................................. 5-10
5.2.6 Interrupt Request Register 01 (IRQ01) ........................................................................................................ 5-12
5.2.7 Interrupt Request Register 23 (IRQ23) ........................................................................................................ 5-14
5.2.8 Interrupt Request Register 45 (IRQ45) ........................................................................................................ 5-16
5.2.9 Interrupt Request Register 67 (IRQ67) ........................................................................................................ 5-18
5.2.10 Interrupt Level Control Enable Register (ILEN) ....................................................................................... 5-20
5.2.11 Current Interrupt Level Management Register (CIL) ................................................................................ 5-21
5.2.12 Interrupt Level Control Register 0 (ILC0) ................................................................................................. 5-22
5.2.13 Interrupt Level Control Register 1 (ILC1) ................................................................................................. 5-23
5.2.14 Interrupt Level Control Register 2 (ILC2) ................................................................................................. 5-25
5.2.15 Interrupt Level Control Register 3 (ILC3) ................................................................................................. 5-27
5.2.16 Interrupt Level Control Register 4 (ILC4) ................................................................................................. 5-29
5.2.17 Interrupt Level Control Register 5 (ILC5) ................................................................................................. 5-31
5.2.18 Interrupt Level Control Register 6 (ILC6) ................................................................................................. 5-33
5.2.19 Interrupt Level Control Register 7 (ILC7) ................................................................................................. 5-35
5.3 Description of Operation ............................................................................................................................. 5-37
5.3.1 Maskable Interrupt Processing ..................................................................................................................... 5-40
5.3.2 Non-Maskable Interrupt Processing ............................................................................................................ 5-40
5.3.3 Software Interrupt Processing ...................................................................................................................... 5-40
FEUL62Q1000
ML62Q1000 Series User's Manual
Contents-2
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