LAPIS Semiconductor ML62Q1000 Series User Manual page 700

Figure 23-3 shows a setting example when one-time A/D conversion is performed in HALT mode using channel 1 and 0.
Set FCON register
Set IE register
Execute EI instruction
Set PnMOD0 to 7 registers
Set VREFCON register
Set SADMOD register
Set SADEN0 register
Set SADLMOD register
Set SADUPL register
Set SADLOL register
Set SADCON register
Set HALT mode
Entering the HALT mode
Interrupt generated?
Release the HALT mode
Read SADRn register
Figure 23-3 Example of A/D Conversion Setting (Converting in HALT mode)
FEUL62Q1000
Chapter 23 Successive Approximation Type A/D Converter
Setting
start
Set the ENOSC bit of the FCON register to "1" to start supplying
the high-speed clock.
The high-speed clock is supplied after the oscillation stabilization
time has passed.
If enabling
register to "1".
Execute the EI instruction to set the master interrupt enable flag (MIE) to "1".
Set the general-purpose port of AINn to the both input and output are
disable.
To use the voltage that is input from the V
voltage, set the mode of that disables the input and disables the output.
Set the mode of the reference voltage.
Set the A/D conversion mode. (SALP = 1)
Set the channel to be A/D-converted. (SADEN0=0x03)
To use the upper/lower limit function for the conversion result, this
setting is required.
Set the start and end of A/D conversion.
When SARUN bit="1", the A/D conversion is started.
Starts A/D conversion
Set ESAD bit of IE23 register to "0".
Set HLT bit(or HLTH bit) of SBYCONL register to "1".
NO
YES
A/D conversion is
completed
End
(SA-ADC interrupt), set the ESAD bit of the IE23
SADINT
The SARUN bit is automatically cleared to "0".
Read the A/D conversion result.
(n=0, 1)
ML62Q1000 Series User's Manual
pin as the reference
REF
23-24