LAPIS Semiconductor ML62Q1000 Series User Manual page 488

When the values of the transmitted bit and the I2CU0_SDA pin do not coincide, the I2US0ER bit of the I
register (I2US0STA) is set to "1" and the I2CU0_SDA pin output is disabled until termination of the subsequent byte
data communication.
Figure 12-10 shows the operation timing and control method when transmission fails.
I2US0RD register
Figure 12-10 Operation Timing When Transmission Fails When Slave Mode is Chosen
[Note]
Ÿ
If entering to the STOP/STOP-D mode while the slave mode is enabled, first make sure that
communication is not in progress (from coincidence of address to reception of stop condition).
FEUL62Q1000
I2US0TD="xxH"
Register
I2US0CON="20H"
setting
D D
I2CU0_SDA pin
7 6
I2CU0INT
I2US0ER bit
Transmission failure
D D D
A
5 4 3
ML62Q1000 Series User's Manual
Chapter 12 I2C Bus Unit
Undefined data
2
C bus 0 status
12-32