LAPIS Semiconductor ML62Q1000 Series User Manual page 21

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Reset
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RESET_N pin reset
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Reset by power-on detection
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Reset by the 2
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Reset by WDT counter clear during the clear invalid period
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Reset by RAM parity error
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Reset by unused ROM access
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Reset by voltage level detection 0 (VLS0)
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The software reset by BRK instruction (reset CPU only)
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Reset to the peripherals by the block reset control registers
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Power management
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HALT mode: CPU stops executing instruction, clock oscillations and peripheral circuits remain previous states
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HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits
working with low-speed clock remain previous states
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STOP mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop.
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STOP-D mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop.
(V ) goes down to reduce the current consumption (RAM data is retained).
DDL
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Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, 1/16 or
1/32 of the oscillation clock)
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Block Control Function: Powers down the circuits of unused function blocks (reset the block or stop supplying
the clock)
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Interrupt controller
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External interrupt : Max. 12
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Non-maskable interrupt source: 1 (Internal sources: WDT)
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Maskable interrupt sources: max.52 (Internal sources: max.40, External sources: 12)
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Four step interrupt levels
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Watchdog timer(WDT)
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Operating clock is selectable (1kHz WDT independent clock or divided clock of internal 32.768kHz RC
oscillation)
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Overflow period: 8 types selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2000ms and
8000ms@32.768kHz)
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Enabling or disabling the window function is selectable (The clear enable period is 50% or 75% of overflow
period)
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WDT operation is selectable by code option (Enable or Disable)
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Readable WDT counter (WDT counter monitor function)
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The first overflow generates the WDT interrupt, and the second overflow generates the WDT reset when the
counter clear enable period is 100% of overflow period
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The first overflow generates the WDT reset when the counter clear enable period is 50% or 75% of overflow
period
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The invalid clear reset generated when the WDT counter is cleared out of the WDT counter clear enable period.
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DMA(Direct Memory Access) controller
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Channel : 2ch
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Transfer unit: 8bit/16bit
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Transfer count: 1 to 1024
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Transfer type: 2 cycle transfer
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Transfer mode: Single transfer mode (Fixed address, address increments and address decrements)
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Transfer target: SFR ßà RAM (Transfer from/to Flash is not supported)
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Transfer request trigger: Serial communication unit, Successive approximation type A/D converter, 16bit timer,
Functional timer and External pin.
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Low-speed Time base counter
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Devide the Low-speed clock(LSCLK) and generate 128Hz to1Hz internal pulse signals
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Three interrupts are selectable out of eight frequency periodical interrupts (128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz,
2Hz and 1Hz)
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The time base clock output (1Hz or 2Hz) from general purpose ports (TBCOUT1).
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Frequency adjust function (Adjust range: approx. -488ppm to +488ppm, adjust resolution: approx. 0.119ppm)
(ML62Q1500 and ML62Q1700 group)
FEUL62Q1000
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watchdog timer (WDT) overflow
ML62Q1000 Group User's Manual
Chapter 1 Overview
1-4