LAPIS Semiconductor ML62Q1000 Series User Manual page 358

6: Choice of the external output signal
FTnOSL1 and FTnOSL0 bits of FTnMOD register are used to choose the positive output signal or negative phase
output signal driven to the FTMnP pin or FTMnN pin.
FTnOSNP bit is used to determine if reversing the signal driven to the FTMnP pin.
FTnOSNN bit is used to determine if reversing the signal driven to the FTMnN pin.
Positive phase
Negative phase
7: Control start/stop
Allow the software start, or event trigger reception, emergency stop setting.
The counter operates at the rising edge of the count clock.
Since the software start/stop is synchronized with the count clock, the FTnSTA bit becomes "1" at the start after one
cycle of the count clock. After two cycles, the counter operation starts.
When the operation is stopped, the count operation stops after one cycle of the count clock and the FTnSTA bit
becomes "0". Then the count value is maintained.
If started again, it restarts after one cycle.
If clearing the counter, write an arbitrary value to the FTnC register.
8: Operation process in progress (FTnSTAT register, FTCSTAT register, FTnINTS register, FTCUD register, FTCCON
register)
The state under operation can be checked by the FTnSTAT, FTCSTAT, and FTnINTS registers.
To change the waveform of PWM, etc., set the applicable bit of the FTMUD register after setting the cycle/event. The
waveform will be updated in the next cycle.
In addition, setting the FTnSDN bit of the FTCCON register forces the output to be fixed to "L" level.
FEUL62Q1000
FTnOSL0
FTnOSL1
Figure 9-2 Configuration of the external output signal control
ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
1
1
0
0
FTnOSNP
1
1
0
0
FTnOSNN
FTMnP pin
FTMnN pin
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