LAPIS Semiconductor ML62Q1000 Series User Manual page 878

See Section 25.3.2 "Programming Program Memory Space".
[ ] Only erase areas irrelevant to program processing. If erasing the area where program processing is in
progress, the LSI works incorrectly.
[ ] During block/sector erase, the CPU stops the operation for maximum 50 ms whereas peripheral
circuits continue operation. Therefore, clear the WDT counter accordingly.
[ ] For block/sector erase, place two NOP instructions following the instruction used to set FERS/FSERS
bits of the FLASHCON register to "1".
[ ] Only erase areas irrelevant to program processing. If erasing the area where program processing is in
progress, the LSI works incorrectly.
[ ] During the programming, the CPU stops the operation for maximum 80 μs whereas peripheral circuits
continue operation. Therefore, clear the WDT counter accordingly.
[ ] For data programming setting, place two NOP instructions following the instruction used to set the
programming data in the FLASHD1 register.
See Section 25.3.3 "Programming Data Flash Area".
[ ] The CPU continues program processing even while data flash erase is in progress. Do not enter the
STOP mode, STOP-D mode or HALT-H mode during the erase. In addition, set the FSELF bit of the
FLASHSLF register to "0" after the erase is completed.
[ ] The data flash area is unreadable during erasing.
[ ] For block/sector erase, place two NOP instructions following the instruction used to set FERS/FSERS
bits of the FLASHCON register to "1".
[ ] The CPU continues program processing even while data flash programming is in progress. Do not
enter the STOP mode, STOP-D mode or HALT-H mode during the programming. In addition, set the
FSELF bit of the FLASHSLF register to "0" (erase/program disabled) after the programming ended.
[ ] The data flash area is unreadable during programming.
[ ] For data programming setting, place two NOP instructions following the instruction used to set the
programming data in the FLASHD0L register.
See Section 25.3.4 "Notes on use of self-programming".
[ ] Set to HSCLK when using the self-programming function. See "Chapter 6 Clock Generation Circuit" for
enabling the high-speed clock oscillation and switching the system clock.
[ ] Data in flash memory is not guaranteed if power outage or forced termination due to a reset occurs.
Perform block/sector erase again then program data.
[ ] Program the program again using on-chip debug emulator (EASE1000) or ISP function, in case the LSI
does not start up due to occurrence of power outage or forced termination during programming.
See Section 25.4.2 "Communication Method".
[ ] The UART communication for the ISP function might be affected due to an error of the baud rate and
slow slope of the signals. Be sure to evaluate the operation.
See Section 25.4.3 "Communication Command".
[ ] Programming the program area is performed in units of four bytes. Set four byte boundaries
(0H/4H/8H/CH) for lower four bits of the address.
[ ] Programming the data area is performed in units of one byte.
See Section 25.4.4 "Transition Command to ISP Mode".
[ ] The transition process from point B to the end of initial setting command (1) shown in the figure 25-6
needs to be completed within 55ms.
See Section 25.4.5.1 "Initial Setting".
[ ] The initialization process needs to be completed within 1000ms.
See Section 25.4.5.2 "Erasing Specified Flash Memory Area".
[ ] The erase process needs to be completed within 500ms.
See Section 25.4.5.3 "Programming to Specified Flash Memory Area".
[ ] The programming process needs to be completed within 500ms. In the case of programming to
multiple addresses, the process from previous setting data to the next setting data or to the end of initial
setting command transmission (7) within 500ms.
FEUL62Q1000
ML62Q1000 Series User's Manual
Appendix E. List of Notes
E-19