LAPIS Semiconductor ML62Q1000 Series User Manual page 467

Bit symbol
Bit no.
name
0 I2UM0EN
[Note]
Ÿ
When using the high-speed clock for the I
frequency depending on the mode and the reference frequency of the PLL oscillation.
When HSCLK = 24MHz
Standard mode: HSCLK to 1/4HSCLK
Fast mode:
1Mbps mode:
When HSCLK = 16MHz
Standard mode: HSCLK to 1/2HSCLK
Fast mode:
1Mbps mode:
FEUL62Q1000
This bit is used to enable the master operation. When "1" is written to this bit, the I2UM0ST
bit can be set and the I2UM0BB bit starts operation. When "0" is written to this bit, the I2C
master stops operation and the I2UM0RD, I2UM0SA, I2UM0TD and I2UM0CON registers
are initialized.
In the case "0" is written to this bit during the communication, initialize the I
reconfigure it.
2
0: Stop the I C master operation (initial value)
2
1: Enable the I C master operation
HSCLK to 1/2HSCLK
HSCLK to 1/2HSCLK
HSCLK
HSCLK
Description
2
C operation, specify the following I
ML62Q1000 Series User's Manual
Chapter 12 I2C Bus Unit
2
C bus unit and
2
C operating clock
12-11