LAPIS Semiconductor ML62Q1000 Series User Manual page 480

12.3.1.7 Data Reception Mode
Data receive mode start
Store each bit of received data
in shift register (8-bit) one by one
Transmit acknowledgment value of
2
I C bus 0 control register (I2UM0CON)
receive register (I2UM0RD)
Data receive mode completed
12.3.1.8 Stop Condition
Generate I
Stop condition completed
(move to start condition or I
FEUL62Q1000
2
Store data in I C bus 0
(move to control register
setting wait state)
Stop condition start
Stop condition request
2
C bus unit 0 interrupt
2
C
operation stop )
ML62Q1000 Series User's Manual
Value (received data) input to I2CU0_SDA pin
is stored in synchronization with rising edge of
transfer clock input to I2CU0_SCL pin in MSB first
Acknowledgment signal is transmitted through hardware
I2UM0ACT bit: Acknowledgment value
Transmitted acknowledgment value is stored in the
I2UM0ACR bit of the I2UM0STA register
Received data is stored from the shift register after
acknowledgment signal is transmitted
I2UM0R7 to I2UM0R0 bits: 8-bit receive data
2
I C bus 0 control register (I2UM0CON) setting wait state
Set I2UM0SP bit of I2UM0CON register to "1".
Output stop condition waveforms to I2CU0_SDA and
I2CU0_SCL pins.
After the stop condition waveform is output,
an interrupt is generated through hardware
Move to start condition or I
Chapter 12 I2C Bus Unit
2
C operation stop (I2UM0EN = 1)
12-24