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1.2
Configuration of Functional Blocks
1.2.1
Block Diagram of ML610Q174
V
DD
V
SS
RESET_N
RESET &
TEST0
TEST1_N
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
V
DDL
V
DD
V
SS
V
REF
10bit-ADC
*3
AIN0 to AIN11
4
＊
CMP0P
4
＊
CMP0M
4
＊
CMP1P
4
＊
CMP1M
*1 Secondary or tertiary function
*2 Select I/O port or LCD driver
*3 Select I/O port or A/D converter input
*4 Select I/O port or Analog comparator input
FEUL610Q174
CPU (nX-U8/100) Large Model
EPSW1～3
GREG
0～15
PSW
Timing
ALU
Controller
Instruction
Decoder
On-Chip
ICE
TEST
INT
1
OSC
INT
4
POWER
INT
6
INT
INT
1
INT
2
CMP
Figure 1-1 Block Diagram of ML610Q174
ELR1～3
ECSR1～3
LR
DSR/CSR
EA
PC
SP
BUS
Controller
Instruction
Register
Data-bus
RAM
4096byte
Interrupt
Controller
TBC
8bit Timer
×6
WDT
BLD
ML610Q174 User's Manual
Chapter 1 Overview
Program
Memory
（Flash）
128Kbyte
INT
2
SCK0*
SSIO
SIN0*
SOUT0*
INT
2
RXD0*
UART
TXD0*
INT
1
SDA*
2
I
C
SCL*
INT
3
PWM4*
PWM
PWM5*
PWM6*
PW45EV0*
PW45EV1*
PW6EV0*
PW6EV1*
INT
4
P00 to P03
P10 to P11
P20 to P23
GPIO
P30 to P35
P36
P40 to P43
P44 to P47
P50 to P51
P52 to P53
P80 to P85
P90 to P91
PC0 to PC7
PD0 to PD7
PF0 to PF7
COM0 to COM3
LCD
SEG0 to SEG7
Driver
SEG8 to SEG23
SEG32 to SEG39
LCD
V
BIAS
1
1
, SCK1*
1
1
, SIN1*
1
1
, SOUT1*
1
1
, RXD1*
1
1
, TXD1*
1
1
1
1
1
1
1
1
1
*3
*3
*3
*2
*2
*2
*2
*2
*2
*2
*2
*2
, V
, V
L1
L2
L3
1-4
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