LAPIS Semiconductor ML62Q1000 Series User Manual page 862

See Section 4.2.5 "Software Reset Control Register (SOFTRCON)".
[ ] Do not enter the standby mode when the SOFTR bit is "1". Ensure the SOFTR bit is "0" before entering
the standby mode.
See Section 4.2.6 "Block Clock Control Register 0 (BCKCON0)".
[ ] To restart the operation of the peripheral circuits, reset them at first by the block reset control register
(BRECON0) and then cancel the reset after enabling the clock supply by the block clock control register
(BCKCON0).
See Section 4.2.7 "Block Clock Control Register 1 (BCKCON1)".
[ ] To restart the operation of the peripheral circuits, reset them at first by the block reset control register
(BRECON1) and then cancel the reset after enabling the clock supply by the block clock control register
(BCKCON1).
See Section 4.2.8 "Block Clock Control Register 2 (BCKCON2)".
[ ] The DCKACC bit can be set to "1" when the multiplication/division library "muldivu8.lib" is not specified
in the target option of the Integrated Development Environment IDEU8.
[ ] To restart the operation of the peripheral circuits, reset them at first by the block reset control register
(BRECON2) and then cancel the reset after enabling the clock supply by the block clock control register
(BCKCON2).
See Section 4.2.9 "Block Clock Control Register 3 (BCKCON3)".
[ ] To restart the operation of the peripheral circuits, reset them at first by the block reset control register
(BRECON3) and then cancel the reset after enabling the clock supply by the block clock control register
(BCKCON3).
See Section 4.2.12 "Block Reset Control Register 2 (BRECON2)".
[ ] The DCKACC bit can be set to "1" when the multiplication/division library "muldivu8.lib" is not specified
in the target option of the Integrated Development Environment IDEU8.
See Section 4.3.6 "Note on Return Operation from Standby Mode".
[ ] The operation of returning the standby mode is caused by the interrupt level (ELEVEL) of the program
status word (PSW), master interrupt enable flag (MIE), the contents of the register (IE0 to IE7),
non-maskable interrupt, or maskable interrupt.
[ ] Since up to two instructions are executed during the period between the release of standby mode and
a transition to interrupt processing, place two NOP instructions next to the instruction set for the standby
mode. When a master interrupt enable (MIE) flag of the program status word (PSW) in the nX-U16/100
CPU core is "1", following the execution of the two NOP instructions, the interrupt transition cycle will be
executed and execution of the instruction for interrupt routine begins. If MIE is "0", following the
execution of the two NOP instructions, the instruction execution is continued from the one that follows
the NOP instruction without transition to the interrupt.
[ ] When the CPU operation mode is "Wait mode", the PLL reference frequency is 24MHz and the MIE bit
is "0", choose 12MHz or slower as the SYSTEMCLK before entering the standby modes.
See Section 4.3.7 "Operation of Each Function in Standby Mode".
[ ] If SYSTEMCLK is switched to high-speed after the STOP/STOP-D mode is released and before the
high-speed clock wake-up time passes, the CPU must wait to run the program because the clock supply
is suspended until the end of the wake-up time.
[ ] If peripheral circuits need to work in the HALT-H mode, choose the low-speed clock for the operating
clock.
[ ] When the FHWUPT register is set to "0x00", the PLL output clock is masked for approx.2.5 ms.
HSCLK will be supplied after the elapse of 2.5 ms. If HSCLK is selected for SYSTEMCLK, the
SYSTEMCLK is stopped for the time period.
[ ] When the FHWUPT register is set to "0x01", the frequency of PLL oscillation clock gradually increases
from approx. 1 MHz after the elapse of the wake-up time chosen by the FHWUPT register and reaches
the target frequency (16 MHz/24 MHz) chosen by the code option before approx. 2 ms elapse. The PLL
oscillation clock during this time period can be used for the SYSTEMCLK, however, accuracy of the
frequency is not guaranteed.
FEUL62Q1000
ML62Q1000 Series User's Manual
Appendix E. List of Notes
E-3