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LAPIS Semiconductor ML610472 User Manual

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FEUL610473-09
ML610471/ML610472/ML610473
ML610Q471/ML610Q472/ML610Q473
User's Manual
Issue Date: Jan. 7, 2013

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Summary of Contents for LAPIS Semiconductor ML610472

  • Page 1 FEUL610473-09 ML610471/ML610472/ML610473 ML610Q471/ML610Q472/ML610Q473 User’s Manual Issue Date: Jan. 7, 2013...
  • Page 2 LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
  • Page 3 Preface This manual describes the operation of the hardware of the 8-bit microcontroller ML610471/ML610472/ML610473/ML610Q471/ML610Q472/ML610Q473. The following manuals are also available. Read them as necessary. nX-U8/100 Core Instruction Manual Description on the basic architecture and the each instruction of the nX-U8/100 Core.
  • Page 4 Notation Classification Notation Description ♦ Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F Indicates a binary number; “b” may be omitted. x: A value 0 or 1 ♦ Unit word, W 1 word = 16 bits byte, B 1 byte = 8 bits...

  • Page 5: Table Of Contents

    1.3.1.1 Pin Layout of ML610471 / ML610Q471 48pin TQFP Package ............. 1-6 1.3.1.2 Pin Layout of ML610471 / ML610Q471 64pin TQFP Package ............. 1-7 1.3.1.3 Pin Layout of ML610472 / ML610Q472 48pin TQFP Package ............. 1-8 1.3.1.4 Pin Layout of ML610472 / ML610Q472 64pin TQFP Package ............. 1-9 1.3.1.5 Pin Layout of ML610473 / ML610Q473 48pin TQFP Package ...........
  • Page 6 ML610Q471/ML610Q472/ML610Q473 User’s Manual Contents 4.1.1 Features ..............................4-1 4.1.2 Configuration ............................4-1 4.2 Description of Registers ..........................4-2 4.2.1 List of Registers ............................. 4-2 4.2.2 Stop Code Acceptor (STPACP) ......................4-3 4.2.3 Standby Control Register (SBYCON) ....................4-4 4.2.4 Block Control Register 0 (BLKCON0)....................4-5 4.2.5 Block Control Register 1 (BLKCON1)....................
  • Page 7 ML610471/ML610472/ML610473 User’s Manual Contents 6.3.1.2 Operation of Low-Speed Clock Generation Circuit ................ 6-6 6.3.2 High-speed clock............................ 6-7 6.3.2.1 High-Speed Clock Circuit........................ 6-7 6.3.2.2 Operation of High-Speed Clock Generation Circuit................ 6-8 6.3.3 Switching of System Clock ........................6-9 6.4 Specifying Port Registers .......................... 6-10 6.4.1 Functioning P21 (OUTCLK) as the high-speed clock output..............
  • Page 8 ML610Q471/ML610Q472/ML610Q473 User’s Manual Contents 9.2.9 Timer 3 Control Register 1 (TM3CON1)..................... 9-11 9.3 Description of Operation ..........................9-12 9.3.1 Timer mode operation .......................... 9-12 9.3.2 16-bit timer frequency measurement mode operation................9-13 9.3.3 16-bit timer frequency measurement mode application for setting uart baud-rate....... 9-15 9.4 Operating Timers by External Clock Inputs ....................
  • Page 9 ML610471/ML610472/ML610473 User’s Manual Contents 12.2 Description of Registers .......................... 12-2 12.2.1 List of Registers ..........................12-2 12.2.2 Port 0 Data Register (P0D) ........................ 12-3 12.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) ................12-4 12.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1) ........... 12-5 12.2.5 External Interrupt Control Register 2 (EXICON2) ................
  • Page 10 ML610Q471/ML610Q472/ML610Q473 User’s Manual Contents 15.3.2 Secondary and Tertiary Functions....................15-10 Chapter 16 16. Port 6 ................................16-1 16.1 General Description..........................16-1 16.1.1 Features .............................. 16-1 16.1.2 Configuration ............................. 16-1 16.1.3 List of Pins ............................16-1 16.2 Description of Registers .......................... 16-2 16.2.1 List of Registers ..........................
  • Page 11 ML610471/ML610472/ML610473 User’s Manual Contents Chapter 19 Power Supply Circuit..........................19-1 19.1 Overview ..............................19-1 19.1.1 Features .............................. 19-1 19.1.2 Configuration ............................. 19-1 19.1.3 List of Pins ............................19-1 Chapter 20 20. uEASE Flash Writer System......................... 20-1 20.1 Overview ..............................20-1 20.2 Method of Connecting to the uEASE ......................

  • Page 12: Overview

    Chapter 1 Overview...

  • Page 13: Features

    30.5 μs (@ 32.768 kHz system clock) 2 μs (@ 500 kHz system clock) Internal memory - ML610471/ML610472/ML610473 Internal 8KByte Mask ROM (4K x 16 bits) (including unusable 256Byte TEST area) Internal 512Byte RAM (512 x 8 bits) - ML610Q471/ML610Q472/ML610Q473...
  • Page 14 General-purpose port - Input-only port: 4 channels (including secondary functions) - Output-only port ML610471/ML610Q471: 10 channels (including secondary functions) ML610472/ML610Q472: 6 channels (including secondary functions) ML610473/ML610Q473: 2 channels (including secondary functions) - Input/output port: 7 channels (including secondary functions) LCD driver...
  • Page 15 - Block control function: Completely stops the operation of any function block circuit that is not used (resets registers and stops clock) Shipment − Chip (Die) ML610471-xxxWA / ML610Q471-xxxWA ML610472-xxxWA / ML610Q472-xxxWA ML610473-xxxWA / ML610Q473-xxxWA ML610471P-xxxWA / ML610Q471P-xxxWA ML610472P-xxxWA / ML610Q472P-xxxWA ML610473P-xxxWA / ML610Q473P-xxxWA −...

  • Page 16: Configuration Of Functional Blocks

    2 commons with the register (*3) Select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22 segments x 2 commons with the register Figure 1-1 Block Diagram of ML610471/ML610472/ML610473...

  • Page 17: Block Diagram Of Ml610Q471/Ml610Q472/Ml610Q473

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.2.2 Block Diagram of ML610Q471/ML610Q472/ML610Q473 CPU (nX-U8/100) EPSW1−3 ELR1−3 ECSR1−3 GREG 0−15 DSR/CSR Timing Controller Program Memory Instruction Instruction Controller (Flash) Flash Decoder Register 8Kbyte Writer Data-bus RESET_N RESET & TEST0 512 byte TEST Interrupt Controller RXD0*...

  • Page 18: Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3 Pins 1.3.1 Pin Layout 1.3.1.1 Pin Layout of ML610471/ML610Q471 48pin TQFP Package SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 NC(*1) / VPP(*2) MIRROR FINISH (NC): No Connection (*1) : ML610471 (*2) : ML610Q471 Figure 1-3 Pin Layout of ML610471/ML610Q471 48pin TQFP Package...

  • Page 19: Pin Layout Of Ml610471/Ml610Q471 64Pin Tqfp Package

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.2 Pin Layout of ML610471/ML610Q471 64pin TQFP Package SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 NC(*1) / VPP(*2) MIRROR FINISH (NC): No Connection (*1) : ML610471 (*2) : ML610Q471 Figure 1-4 Pin Layout of ML610471/ML610Q471 64pin Package...

  • Page 20: Pin Layout Of Ml610472/Ml610Q472 48Pin Tqfp Package

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.3 Pin Layout of ML610472/ML610Q472 48pin TQFP Package SEG17 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 NC(*1) / VPP(*2) MIRROR FINISH (NC): No Connection (*1) : ML610472 (*2) : ML610Q472 Figure 1-5 Pin Layout of ML610472/ML610Q472 48pin Package...

  • Page 21: Pin Layout Of Ml610472/Ml610Q472 64Pin Tqfp Package

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.4 Pin Layout of ML610472/ML610Q472 64pin TQFP Package SEG17 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 NC(*1) / VPP(*2) MIRROR FINISH (NC): No Connection (*1) : ML610472 (*2) : ML610Q472 Figure 1-6 Pin Layout of ML610472/ML610Q472 64pin Package...

  • Page 22: Pin Layout Of Ml610473/Ml610Q473 48Pin Tqfp Package

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.5 Pin Layout of ML610473/ML610Q473 48pin TQFP Package SEG17 SEG4 SEG18 SEG3 SEG19 COM4/SEG2 COM3/SEG1 SEG20 SEG21 COM2/SEG0 COM1 COM0 NC(*1) / VPP(*2) MIRROR FINISH (NC): No Connection (*1) : ML610473 (*2) : ML610Q473 Figure 1-7 Pin Layout of ML610473/ML610Q473 48pin Package 1-10...

  • Page 23: Pin Layout Of Ml610473/Ml610Q473 64Pin Tqfp Package

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.6 Pin Layout of ML610473/ML610Q473 64pin TQFP Package SEG17 SEG4 SEG18 SEG3 SEG19 COM4/SEG2 COM3/SEG1 SEG20 SEG21 COM2/SEG0 COM1 COM0 NC(*1) / VPP(*2) MIRROR FINISH (NC): No Connection (*1) : ML610473 (*2) : ML610Q473 Figure 1-8 Pin Layout of ML610473/ML610Q473 64pin Package 1-11...

  • Page 24: Pin Layout Of Ml610471 Chip

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.7 Pin Layout of ML610471 Chip SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 1.77mm 1.61mm Chip size: 1.61 mm × 1.77 mm PAD count: 49 pins Minimum PAD pitch: 80μm PAD aperture: 70μm×70μm Chip thickness: 350μm Voltage of the rear side of chip: V level.

  • Page 25: Pin Layout Of Ml610472 Chip

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.8 Pin Layout of ML610472 Chip SEG4 SEG17 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 1.77mm 1.61mm Chip size: 1.61 mm × 1.77 mm PAD count: 49 pins Minimum PAD pitch: 80μm PAD aperture: 70μm×70μm Chip thickness: 350μm...

  • Page 26: Pin Layout Of Ml610473 Chip

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.9 Pin Layout of ML610473 Chip SEG4 SEG17 SEG3 SEG18 COM4/SEG2 SEG19 COM3/SEG1 SEG20 COM2/SEG0 SEG21 COM1 COM0 1.77mm 1.61mm Chip size: 1.61 mm × 1.77 mm PAD count: 49 pins Minimum PAD pitch: 80 μm PAD aperture: 70 μm×70 μm Chip thickness: 350 μm Voltage of the rear side of chip: V...

  • Page 27: Pin Layout Of Ml610Q471 Chip

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.10 Pin Layout of ML610Q471 Chip SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 1.88mm VPP 50 1.95mm (NC): No Connection Chip size: 1.95 mm × 1.88 mm PAD count: 50 pins Minimum PAD pitch: 80μm PAD aperture: 70μm×70μm Chip thickness: 350μm Voltage of the rear side of chip: V...

  • Page 28: Pin Layout Of Ml610Q472 Chip

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.11 Pin Layout of ML610Q472 Chip SEG17 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 1.88mm VPP 50 1.95mm (NC): No Connection Chip size: 1.95 mm × 1.88 mm PAD count: 50 pins Minimum PAD pitch: 80μm PAD aperture: 70μm×70μm Chip thickness: 350μm Voltage of the rear side of chip: V...

  • Page 29: Pin Layout Of Ml610Q473 Chip

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.12 Pin Layout of ML610Q473 Chip SEG17 SEG4 SEG3 SEG18 COM4/SEG2 SEG19 COM3/SEG1 SEG20 COM2/SEG0 SEG21 COM1 COM0 1.88mm VPP 50 1.95mm (NC): No Connection Chip size: 1.95 mm × 1.88 mm PAD count: 50 pins Minimum PAD pitch: 80 μm PAD aperture: 70 μm×70 μm Chip thickness: 350 μm...

  • Page 30: Pad Coordinates Of Ml610471/Ml610472/M610473 Chip

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.13 Pad Coordinates of ML610471/ML610472/M610473 Chip Table 1-1 Pad Coordinates of ML610471/ML610472/ML610473 Chip Center: X=0,Y=0 ML610471/2/3 ML610471/2/3 Name X (μm) Name Y (μm) X (μm) Y (μm) -779 SEG10 -410 -779 SEG11 -330 VDDL...

  • Page 31: Pad Coordinates Of Ml610Q471/Ml610Q472/M610Q473 Chip

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.1.14 Pad Coordinates of ML610Q471/ML610Q472/M610Q473 Chip Table 1-2 Pad Coordinates of ML610Q471/ML610Q472/ML610Q473 Chip Center: X=0,Y=0 ML610Q471/2/3 ML610Q471/2/3 Name X (μm) Name Y (μm) X (μm) Y (μm) -834 SEG10 -580 -834 SEG11 -500 VDDL -834 SEG12 -420...

  • Page 32: List Of Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.2 List of Pins PIN No. Primary function Secondary function (*1) (*2) Pin name Function Pin name Function (MASK) (FLASH) ⎯ ⎯ ⎯ ⎯ Negative power supply pin (*3) ⎯ ⎯ ⎯ ⎯ Positive power supply pin Power supply pin for internal ⎯...
  • Page 33 LCD segment pin Output port ⎯ ⎯ ⎯ (*4) (*5) (*6) ⎯ ⎯ ⎯ SEG21 LCD segment pin (*1) (*2) 48pin TQFP. 64pin TQFP (*3) Pad for ML610Q471/ML610Q472/ML610Q473 (*4) Pad for ML610471/ML610Q471. (*5) Pad for ML610472/ML610Q472. (*6) Pad for ML610473/ML610Q473. 1-21...

  • Page 34: Pin Descriptions

    This cannot be used as the general input/output port when used as the secondary function. P60 to P63 General-purpose output port. Incorporated only into Primary Positive ML610471/610Q471/ML610472/ML610Q472, and not into ML610473/ML610Q473 P64 to P67 General-purpose output port. Primary Positive Incorporated only into ML610473/ML610Q473, and not into ML610471/ML610Q471/ML610472/ ML610Q472.
  • Page 35 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview Primary/ Pin name Description Logic Secondary Capture CAP0 Capture trigger input pins. The value of the time base counter is Primary Positive/ captured in the register synchronously with the interrupt edge negative selected by software. These pins are used as the primary functions CAP1 Primary Positive/...
  • Page 36 — SEG13 switching the register setting with the COM2, COM3, and COM4. SEG14 to Segment output pin. Incorporated into — — SEG17 ML610472/ML610Q472/ML610473/ML610Q473, not into ML610471/ML610Q471. SEG18 to Segment output pin. Incorporated into ML610473/ML610Q473, not — — SEG21 into ML610471/ML610Q471/ML610472/ML610Q472.

  • Page 37: Handling Of Unused Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 1 Overview 1.3.4 Handling of Unused Pins Table 1-3 shows methods of terminating the unused pins. Table 1-3 Termination of Unused Pins Recommended pin handling Open Open Open Open C1, C2 Open RESET_N Open TEST0 Pull down(1kΩ to VSS) VDD or VSS P20, P21 Open...

  • Page 38: Cpu And Memory Space

    Chapter 2 CPU and Memory Space...

  • Page 39: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 2 CPU and Memory Space 2. CPU and Memory Space Overview This LSI includes 8-bit CPU nX-U8/100 and the memory model is SMALL model. For details of the CPU nX-U8/100, see “nX-U8/100 Core Instruction Manual”. Program Memory Space The program memory space is used to store program codes, table data (ROM window), or vector tables.

  • Page 40: Data Memory Space

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 2 CPU Data Memory Space The data memory space of this LSI consists of the ROM window area, 512Byte RAM area, and SFR area of Segment 0. The data memory has the 8-bit length and is specified by the addressing specified by each instruction. Figure 2-2 shows the configuration of the data memory space.

  • Page 41: Instruction Length

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 2 CPU and Memory Space Instruction Length The length of an instruction is 16 bits. Data Type The data types supported include byte (8 bits) and word (16 bits).

  • Page 42: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 2 CPU Description of Registers 2.6.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F000H Data segment register —...

  • Page 43: Data Segment Register (Dsr)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 2 CPU and Memory Space 2.6.2 Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8-bit Initial value: 00H — — — — DSR3 DSR2 DSR1 DSR0 Initial value DSR is a special function register (SFR) to retain a data segment. Always use this register with the initial state (0).

  • Page 44: Reset Function

    Chapter 3 Reset Function...

  • Page 45: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 3 Reset Function 3. Reset Function Overview This LSI has the five reset functions shown below. If any of the five reset conditions is satisfied, this LSI enters system reset mode. • Reset by the RESET_N pin •...

  • Page 46: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 3 Reset Function 3.2 Description of Registers 3.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value ⎯ 0F001H Reset status register RSTAT — 3.2.2 Reset Status Register (RSTAT) Address: 0F001H Access: R/W Access size: 8-bit Initial value: Undefined ⎯...

  • Page 47: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 3 Reset Function 3.3 Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all the processings and any other processing being executed up to then is cancelled. The system reset mode is set by any of the following causes. •...

  • Page 48: Mcu Control Function

    Chapter 4 MCU Control Function...

  • Page 49: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4. MCU Control Function 4.1 Overview The operating states of this LSI are classified into the following 4 modes including system reset mode: (1) System reset mode (2) Program run mode (3) HALT Mode (4) STOP mode For system reset mode, see Chapter 3, “Reset Function”.

  • Page 50: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.2 Description of Registers 4.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F008H Stop code acceptor STPACP — — 0F009H Standby control register SBYCON — 0F028H Block control register 0 BLKCON0 —...

  • Page 51: Stop Code Acceptor (Stpacp)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.2.2 Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8-bit Initial value:—(Undefined) STPACP — — — — — — — — Initial value STPACP is a write-only special function register (SFR) that is used for setting a STOP mode. When STPACP is read, “00H”...

  • Page 52: Standby Control Register (Sbycon)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8-bit Initial value: 00H SBYCON — — — — — — Initial value SBYCON is a special function register (SFR) to control operating mode of MCU. [Description of Bits] •...

  • Page 53: Block Control Register 0 (Blkcon0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.2.4 Block Control Register 0 (BLKCON0) Address: 0F028H Access: R/W Access size: 8-bit Initial value: 00H BLKCON0 — — — — DTM3 DTM2 — — Initial value BLKCON0 is a special function register (SFR) to control each block operation. [Description of Bits] •...

  • Page 54: Block Control Register 1 (Blkcon1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.2.5 Block Control Register 1 (BLKCON1) Address: 0F029H Access: R/W Access size: 8-bit Initial value: 00H BLKCON1 — DCAPR — — — — — — Initial value BLKCON1 is a special function register (SFR) to control each block operation. [Description of Bits] •...

  • Page 55: Block Control Register 2 (Blkcon2)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.2.6 Block Control Register 2 (BLKCON2) Address: 0F02AH Access: R/W Access size: 8-bit Initial value: 00H BLKCON2 — — — — — DUA0 — — Initial value BLKCON2 is a special function register (SFR) to control each block operation. [Description of Bits] •...

  • Page 56: Block Control Register 4 (Blkcon4)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.2.7 Block Control Register 4 (BLKCON4) Address: 0F02CH Access: R/W Access size: 8-bit Initial value: 00H BLKCON4 — DLCD — — — — DRAD — Initial value BLKCON4 is a special function register (SFR) to control each block operation. [Description of Bits] •...

  • Page 57: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.3 Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, low-speed oscillation stop detect reset, WDT overflow reset, or RESET_N pin reset, the CPU executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system reset mode is released.

  • Page 58: Stop Mode

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.3.3 STOP mode The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by writing “5nH”(n: an arbitrary value) and “0AnH”(n: an arbitrary value) to the stop code acceptor (STPACP) sequentially and the STP bit of the standby control register (SBYCON) is set to “1”, the STOP mode is entered.

  • Page 59: Stop Mode When Cpu Operates With High-Speed Clock

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock When the CPU is operating with the high-speed clock and the STP bit of SBYCON is set to “1” with the stop code acceptor enabled, the STOP mode is entered and high-speed oscillation and low-speed oscillation stop.

  • Page 60: Note On Return Operation From Stop/Halt Mode

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.3.4 Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.

  • Page 61: Block Control Function

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 4 MCU Control Function 4.3.5 Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. For each block control register, the initial value of each flag is "0", meaning the operation of each block is enabled. When any flag is set to "1"...

  • Page 62: Interrupts

    Chapter 5 Interrupts...

  • Page 63: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5. Interrupts 5.1 Overview This LSI has 13 interrupt sources (External interrupts: 4 sources, Internal interrupts: 9 sources) and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 7, “Time Base Counter” Chapter 9, “Timer”...

  • Page 64: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2 Description of Registers 5.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F011H Interrupt enable register 1 — 0F014H Interrupt enable register 4 — 0F015H Interrupt enable register 5 —...

  • Page 65: Interrupt Enable Register 1 (Ie1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.2 Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8-bit Initial value: 00H — — — — EP03 EP02 EP01 EP00 Initial value IE1 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE1 is not reset.

  • Page 66: Interrupt Enable Register 4 (Ie4)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.3 Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8-bit Initial value: 00H — — ERAD — — — — EUA0 Initial value IE4 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE4 is not reset.

  • Page 67: Interrupt Enable Register 5 (Ie5)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.4 Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8-bit Initial value: 00H — — ETM3 ETM2 — — — — Initial value IE5 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE5 is not reset.

  • Page 68: Interrupt Enable Register 6 (Ie6)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.5 Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8-bit Initial value: 00H E32H — E128H — — — — — Initial value IE6 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE6 is not reset.

  • Page 69: Interrupt Enable Register 7 (Ie7)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.6 Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8-bit Initial value: 00H — — — — — — E16H Initial value IE7 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE7 is not reset.

  • Page 70: Interrupt Request Register 0 (Irq0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.7 Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8-bit Initial value: 00H IRQ0 — — — — — — — QWDT Initial value IRQ0 is a special function register (SFR) to request an interrupt for each interrupt source. The watchdog timer interrupt (WDTINT) is a non-maskable interrupt that do not depend on MIE.

  • Page 71: Interrupt Request Register 1 (Irq1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.8 Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8-bit Initial value: 00H IRQ1 — — — — QP03 QP02 QP01 QP00 Initial value IRQ1 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ1 request flag is set to “1”...

  • Page 72: Interrupt Request Register 4 (Irq4)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.9 Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8-bit Initial value: 00H IRQ4 — — QRAD — — — — QUA0 Initial value IRQ4 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ4 request flag is set to “1”...

  • Page 73: Interrupt Request Register 5 (Irq5)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.10 Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8-bit Initial value: 00H IRQ3 — — QTM3 QTM2 — — — — Initial value IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ5 request flag is set to “1”...

  • Page 74: Interrupt Request Register 6 (Irq6)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.11 Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8-bit Initial value: 00H IRQ6 Q32H — Q128H — — — — — Initial value IRQ6 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ6 request flag is set to “1”...

  • Page 75: Interrupt Request Register 7 (Irq7)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.2.12 Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8-bit Initial value: 00H IRQ7 — — — — — — Q16H Initial value IRQ7 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ7 request flag is set to “1”...

  • Page 76: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.3 Description of Operation With the exception of the watchdog timer interrupt (WDTINT), interrupt enable/disable for 20 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE1 to 7). WDTINT is a non-maskable interrupt.

  • Page 77: Maskable Interrupt Processing

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.3.1 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) Transfer the program counter (PC) to ELR1 (2) Transfer CSR to ECSR1 (3) Transfer PSW to EPSW1 (4) Set the MIE flag to “0”...

  • Page 78: Notes On Interrupt Routine

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.3.4 Notes on Interrupt Routine Notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable.
  • Page 79 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled •Processing immediately after the start of interrupt routine execution Specify the “PUSH LR” instruction to save the subroutine return address in the stack. •Processing at the end of interrupt routine execution Specify “POP LR”...
  • Page 80 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt Status B: Non-maskable interrupt is being processed B-1: When a subroutine is not called in an interrupt routine •Processing immediately after the start of interrupt routine execution Specify "PUSH ELR, EPSW" to save the interrupt return address and the PSW status in the stack. •Interrupt routine execution end processing Specify "POP PSW, PC"...

  • Page 81: Interrupt Disable State

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 5 Interrupt 5.3.5 Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state. Interrupt disabled state 1:Between the interrupt shift cycle and the instruction at the beginning of the interrupt routine When the interrupt conditions are satisfied in this section, an interrupt is generated immediately following the execution of the instruction at the beginning of the interrupt routine corresponding to the interrupt that has already...

  • Page 82: Clock Generation Circuit

    Chapter 6 Clock Generation Circuit...

  • Page 83: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6. Clock Generation Circuit 6.1 Overview The clock generation circuit generates and provides a low-speed clock (LSCLK), the low-speed double clock (LSCLK x 2), a high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK). LSCLK, LSCLK x 2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU, and OUTCLK is a clock that is output from a port.

  • Page 84: List Of Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Input/o Pin name Function utput Pin for connecting a crystal for low-speed clock. Pin for connecting a crystal for low-speed clock. 6.2 Description of Registers 6.2.1 List of Registers Initial Address Name...

  • Page 85: Frequency Control Register 0 (Fcon0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.2.2 Frequency Control Register 0 (FCON0) Address: 0F002H Access: R/W Access size: 8/16 bit Initial value: 33H FCON0 OUTC1 OUTC0 SYSC1 SYSC0 — — — — Initial value FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. [Description of Bits] •...

  • Page 86: Frequency Control Register 1 (Fcon1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 1 (FCON1) Address: 0F003H Access: R/W Access size: 8-bit Initial value: 00H FCON1 ENMLT ENOSC SYSCLK — — — — — Initial value FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. [Description of Bits] •...

  • Page 87: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.3 Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Clock Generation Circuit Figure 6-2 shows the circuit configuration of the low-speed clock generation circuit. For the low-speed clock generation circuit, externally provide a 32.768kHz crystal oscillator and capacitors (C In the STOP mode, the XT0 and XT1 pins become Hiz (high-impedance).

  • Page 88: Operation Of Low-Speed Clock Generation Circuit

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.3.1.2 Operation of Low-Speed Clock Generation Circuit The low-speed clock generation circuit is activated by the occurrence of power ON reset. After the power-on, it waits for the low-speed oscillation start time (T ) and the low-speed clock (LSCLK) oscillation stabilization time (8192 counts).

  • Page 89: High-Speed Clock

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.3.2 High-speed clock The high-speed clock is supplied from the 500kHz RC oscillator circuit. 6.3.2.1 High-Speed Clock Circuit After the oscillation is enabled (ENOSC set to "1"), the high-speed clock (OSCLK) supply starts in 16 counts of the RC oscillation clock.

  • Page 90: Operation Of High-Speed Clock Generation Circuit

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.3.2.2 Operation of High-Speed Clock Generation Circuit The high-speed clock generation circuit allows the start/stop control of oscillation by using the frequency control registers 0 and 1 (FCON0 and FCON1). Oscillation can be started by setting the ENOSC bit of FCON1 to "1" after selecting a high-speed oscillation frequency with FCON0.

  • Page 91: Switching Of System Clock

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.3.3 Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-6 shows the flow chart of system clock switching processing (HSCLK to LSCLK) and Figure 6-7 shows the flow chart of system clock switching processing (LSCLK to HSCLK).

  • Page 92: Specifying Port Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.4 Specifying Port Registers To enable the clock output function, each related port register bit needs to be set. See Chapter 15, "Port 2" for detail about the port registers. 6.4.1 Functioning P21 (OUTCLK) as the high-speed clock output Set P21MD bit (bit1 of P2MOD register) to “1”...

  • Page 93: Functioning P20 (Lsclk) As The Low-Speed Clock Output

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 6 Clock Generation Circuit 6.4.2 Functioning P20 (LSCLK) as the low-speed clock output Set P20MD bit (bit0 of P2MOD register) to “1” for specifying the low-speed clock output as the secondary function of P22. Register P2MOD register (Address: 0F214H) name P21MD Bit name...

  • Page 94: Time Base Counter

    Chapter 7 Time Base Counter...

  • Page 95: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter Time Base Counter 7.1 Overview This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base clocks for peripheral circuits. By using the time base counter, it is possible to generate events periodically. For input clocks, see Chapter 6, “Clock Generation Circuit”.
  • Page 96 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter HTBDR HSCLK HTBCLK 1/n-Counter (500kHz) .500khz to 31kHz RESET (Internal signal) Data bus HTBDR : High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK changes according to specified data in SYSC1 and SYSC0 bits of Frequency control register 0 (FCON0).

  • Page 97: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter 7.2 Description of Registers 7.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F00AH Low-speed time base counter register LTBR ― High-speed time base counter 0F00BH HTBDR ― frequency divide register Low-speed time base counter 0F00CH...

  • Page 98: Low-Speed Time Base Counter Register (Ltbr)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter Register (LTBR) Address: 0F00AH Access: R/W Access size: 8-bit Initial value: 00H LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ Initial value LTBR is a special function register (SFR) to read the T128HZ to T1HZ outputs of the low-speed time base counter. The T128HZ-T1HZ outputs are set to “0”...

  • Page 99: High-Speed Time Base Counter Divide Register (Htbdr)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter 7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) Address: 0F00BH Access: R/W Access size: 8-bit Initial value: 00H HTBDR ― ― ― ― HTD3 HTD2 HTD1 HTD0 Initial value HTBDR is a special function register (SFR) to set the dividing ratio of the 4-bit, 1/n counter. [Description of Bits] •...

  • Page 100: Low-Speed Time Base Counter Frequency Adjustment Registers L And H (Ltbadjl, Ltbadjh)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter 7.2.4 Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH) Address: 0F00CH Access: R/W Access size: 8/16 bit Initial value: 00H LTBADJL LADJ7 LADJ6 LADJ5 LADJ4 LADJ3 LADJ2 LADJ1 LADJ0 Initial value Address: 0F00DH...

  • Page 101: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter 7.3 Description of Operation 7.3.1 Low-speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The T128HZ, T32HZ, T16HZ, and T2HZ outputs of LTBC are used as time base interrupts and an interrupt is requested on the falling edge of each output.

  • Page 102: High-Speed Time Base Counter

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter 7.3.2 High-Speed Time Base Counter The high-speed time base counter is configured as a 4-bit 1/n counter (n = 1 to 16). In the 4-bit 1/n counter, the divided clock (1/16 x HSCLK to 1/1 x HSCLK) selected by the high-speed time base counter divide register (HTBDR) is generated as HTBCLK.

  • Page 103: Low-Speed Time Base Counter Frequency Adjustment Function

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter 7.3.3 Low-Speed Time Base Counter Frequency Adjustment Function Frequency adjustment (Adjustment range: Approx. -488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm) is possible for outputs of T8KHZ to T1HZ of LTBC by using the low-speed time base counter frequency adjust registers (LTBADJH and LTBADJL).

  • Page 104: A Signal Generation For 16-Bit Timer 2-3 Frequency Measurement Mode

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 7 Time Base Counter 7.3.4 A signal generation for 16-bit timer 2-3 frequency measurement mode A signal (437C) used for 16-bit timer 0-1 frequency measurement mode is generated from the output clock of the low-speed time base counter. See Chapter 9, “Timer” for more detail about the frequency measurement mode. エラー! 参照元が見つかりません。...

  • Page 105: Capture

    Chapter 8 Capture...

  • Page 106: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 8 Capture 8. Capture 8.1 Overview This LSI has two channels of capture circuits that capture the T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) to the capture data register at the occurrence of P00 and P01 interrupts. The circuits capture timings at which each interrupt occurred, based on the time from the time base counter.

  • Page 107: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 8 Capture 8.2 Description of Registers 8.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F090H Capture control register CAPCON — 0F091H Capture status register CAPSTAT — 0F092H Capture data register 0 CAPR0 —...

  • Page 108: Capture Control Register (Capcon)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 8 Capture 8.2.2 Capture Control Register (CAPCON) Address: 0F090H Access: R/W Access size: 8-bit Initial value: 00H CAPCON — — — — — — ECAP1 ECAP0 Initial value CAPCON is a special function register (SFR) to control the capture circuit. [Description of Bits] •...

  • Page 109: Capture Status Register (Capstat)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 8 Capture 8.2.3 Capture Status Register (CAPSTAT) Address: 0F091H Access: R Access size: 8-bit Initial value: 00H CAPSTAT — — — — — — CAPF1 CAPF0 Initial value CAPSTAT is a read-only, special function register (SFR) to indicate a state of the capture circuit. [Description of Bits] •...

  • Page 110: Capture Data Register 0 (Capr0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 8 Capture 8.2.4 Capture Data Register 0 (CAPR0) Address: 0F092H Access: R/W Access size: 8-bit Initial value: 00H CAPR0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Initial value CAPR0 is a register in which capture data is stored. The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P00 interrupt request is generated with the CAPF0 flag (bit 0 of the CAPSTAT register) set to "0".

  • Page 111: Capture Data Register 1 (Capr1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 8 Capture 8.2.5 Capture Data Register 1 (CAPR1) Address: 0F093H Access: R/W Access size: 8-bit Initial value: 00H CAPR1 CP17 CP16 CP15 CP14 CP13 CP12 CP11 CP10 Initial value CAPR1 is a register in which capture data is stored. The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P01 interrupt request is generated with the CAPF1 flag (bit 1 of the CAPSTAT register) set to "0".

  • Page 112: Capture Time Base Data Register (Captb)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 8 Capture 8.2.6 Capture Time Base Data Register (CAPTB) Address: 0F094H Access: R Access size: 8-bit Initial value: Undefined CAPTB CPTB7 CPTB6 CPTB5 CPTB4 CPTB3 CPTB2 CPTB1 CPTB0 Initial value CAPTB is a special function register (SFR) to read the T4KHZ to T32HZ outputs of the low-speed time base counter (LTBC).

  • Page 113: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 8 Capture 8.3 Description of Operation The capture circuit starts the capture operation by setting the ECAP0 or ECAP1 bit of the capture control register (CAPCON). When the input trigger from the P00 or P01 pin selected by the external interrupt control register 0 or 1 (EXICON0 or EXICON1) is generated and the P00 or P01 interrupt request flag (QP00 or QP01) is set to “1”, the T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured in the capture data register 0 or 1 (CAPR0 or CAPR1) on the next low-speed clock (LSCLK) falling edge and the at the same time, the capture flag (CAPF0 or CAPF1) of the...

  • Page 114: Timer

    Chapter 9 Timer...

  • Page 115: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9. Timer 9.1 Overview This LSI includes 2 channels of 8-bit timers. For input clocks, see Chapter 6, “Clock Generation Circuit”. 9.1.1 Features • The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=2, 3) and timer data register (TMnD) coincide.

  • Page 116: List Of Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer Low-speed time base counter (LTBC) 16KHz 8KHz Counter 436cycle 4KHz 2KHz 32KHz 1KHz Decoder 512Hz 256Hz 128Hz 64Hz TM3NT Write TM2C Write TM3C 64Hz 437c LSCLK T2CK TM2CON0 HTBCLK TM2C TM3C External clock TM2CON1 P44/T2CK Read TM2C TM3C latch...

  • Page 117: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2 Description of Registers 9.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F038H Timer 2 data register TM2D 8/16 0FFH TM2DC 0F039H Timer 2 counter register TM2C 0F03AH Timer 2 control register 0 TM2CON0 8/16 0A0H...

  • Page 118: Timer 2 Data Register (Tm2D)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2.2 Timer 2 Data Register (TM2D) Address: 0F038H Access: R/W Access size: 8-bit Initial value: 0FFH TM2D T2D7 T2D6 T2D5 T2D4 T2D3 T2D2 T2D1 T2D0 Initial value TM2D is a special function register (SFR) to set the value to be compared with the value of the timer 2 counter register (TM2C).

  • Page 119: Timer 3 Data Register (Tm3D)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2.3 Timer 3 Data Register (TM3D) Address: 0F03CH Access: R/W Access size: 8-bit Initial value: 0FFH TM3D T3D7 T3D6 T3D5 T3D4 T3D3 T3D2 T3D1 T3D0 Initial value TM3D is a special function register (SFR) to set the value to be compared with the value of the timer 3 counter register (TM3C).

  • Page 120: Timer 2 Counter Register (Tm2C)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2.4 Timer 2 Counter Register (TM2C) Address: 0F039H Access: R/W Access size: 8-bit Initial value: 00H TM2C T2C7 T2C6 T2C5 T2C4 T2C3 T2C2 T2C1 T2C0 Initial value TM2C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM2C is performed, TM2C is set to “00H”.

  • Page 121: Timer 3 Counter Register (Tm3C)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2.5 Timer 3 Counter Register (TM3C) Address: 0F03DH Access: R/W Access size: 8-bit Initial value: 00H TM3C T3C7 T3C6 T3C5 T3C4 T3C3 T3C2 T3C1 T3C0 Initial value TM3C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM3C is performed, TM3C is set to “00H”.

  • Page 122: Timer 2 Control Register 0 (Tm2Con0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2.6 Timer 2 Control Register 0 (TM2CON0) Address: 0F03AH Access: R/W Access size: 8-bit Initial value: A0H TM2CON0 T2FMA7 T2FMA6 T2FMA5 T2FMA4 T23MFM T23M16 T2CS1 T2CS0 Initial value TM2CON0 is a special function register (SFR) to control the Timer 2. Rewrite TM2CON0 while the timer 2 is stopped (T2STAT of the TM2CON1 register is “0”).

  • Page 123: Timer 3 Control Register 0 (Tm3Con0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2.7 Timer 3 Control Register 0 (TM3CON0) Address: 0F03EH Access: R/W Access size: 8-bit Initial value: 00H TM3CON0 — — — — — — T3CS1 T3CS0 Initial value TM3CON0 is a special function register (SFR) to control the Timer 3. Rewrite TM3CON0 while the timer 3 is stopped (T3STAT of the TM3CON1 register is “0”).

  • Page 124: Timer 2 Control Register 1 (Tm2Con1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2.8 Timer 2 Control Register 1 (TM2CON1) Address: 0F03BH Access: R/W Access size: 8-bit Initial value: 00H TM2CON1 T2STAT — — — — — — T2RUN Initial value TM2CON1 is a special function register (SFR) to control the Timer 2. [Description of Bits] •...

  • Page 125: Timer 3 Control Register 1 (Tm3Con1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.2.9 Timer 3 Control Register 1 (TM3CON1) Address: 0F03FH Access: R/W Access size: 8-bit Initial value: 00H TM3CON1 T3STAT — — — — — — T3RUN Initial value TM3CON1 is a special function register (SFR) to control the Timer 3. [Description of Bits] •...

  • Page 126: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.3 Description of Operation 9.3.1 Timer mode operation The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer clocks (TnCK) that are selected by the Timer 2, Timer 3 control register 0 (TMnCON0) when the TnRUN bits of Timer 2, Timer 3 control register 1 (TMnCON1) are set to “1”...

  • Page 127: 16-Bit Timer Frequency Measurement Mode Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.3.2 16-bit timer frequency measurement mode operation The frequency measurement mode in 16-bit timer 2&3, is used to count the frequency of 500kHz RC oscillation clock which typically has temperature variation and production tolerance. Using the frequency measurement mode can make better accuracy for uart baud-rate clock or timer function.
  • Page 128 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer (7) When (T23MFM bit == "1") and (TM23M16 bit == "1") and (T2RUN bit == "1"), the count up starts with the falling of the 64Hz clock signal. (8) The count-up stops at the falling edge of the next timer clock (HTBCLK) after 437C signal becomes “1”. Also, at the same time, T2RUN bit and T2STAT bit become “0”...

  • Page 129: 16-Bit Timer Frequency Measurement Mode Application For Setting Uart Baud-Rate

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.3.3 16-bit timer frequency measurement mode application for setting uart baud-rate For example, when the target baud-rate is 9600bps and the clock is HSCLK(500kHz), the UART0 baud-rate register (UA0BRTH, UA0BRTL) should be set as: UA0BRTH, UA0BRTL = 500000/9600 –...

  • Page 130: Operating Timers By External Clock Inputs

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.4 Operating Timers by External Clock Inputs When the external clock is selected as the operation clock for the Timer 2 (8-bit timer mode), operate it by inputting the clock from the P44 set to the 1st function. When the external clock is selected as the operation clock for the Timer 3 (8-bit timer mode), operate it by inputting the clock with the P45 set to the 1st function.

  • Page 131: Operating Timer 3 (8-Bit Timer Mode) By External Clock (P45/T3Ck)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.4.2 Operating Timer 3 (8-Bit Timer Mode) by External Clock (P45/T3CK) Set the P45MD1 bit (P4MOD1 register's bit 5) to "0" and the P45MD0 bit (P4MOD0 register's bit 5) to "0" for specifying the P45 to the 1st function. Register P4MOD1 register (Address: 0F225H) name...

  • Page 132: Operating Timer 2 And Timer 3 (16-Bit Timer Mode) By External Clock (P44/T2Ck)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 9 Timer 9.4.3 Operating Timer 2 and Timer 3 (16-Bit Timer Mode) by External Clock (P44/T2CK) Set the P44MD1 bit (P4MOD1 register's bit 4) to "0" and the P44MD0 bit (P4MOD0 register's bit 4) to "0" for specifying the P44 to the 1st function.

  • Page 133: Watchdog Timer

    Chapter 10 Watchdog Timer...

  • Page 134: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 10 Watchdog Timer 10. Watchdog Timer 10.1 Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period, the watchdog timer requests a WDT interrupt (non-maskable interrupt).

  • Page 135: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 10 Watchdog Timer 10.2 Description of Registers 10.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F00EH Watchdog timer control register WDTCON — 0F00FH Watchdog timer mode register WDTMOD — 10-2...

  • Page 136: Watchdog Timer Control Register (Wdtcon)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 10 Watchdog Timer 10.2.2 Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: R/W Access size: 8-bit Initial value: 00H WDTCON WDP/d0 Initial value WDTCON is a special function register (SFR) to clear the WDT counter. When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0. [Description of Bits] •...

  • Page 137: Watchdog Timer Mode Register (Wdtmod)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 10 Watchdog Timer 10.2.3 Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: R/W Access size: 8-bit Initial value: 02H WDTMOD — — — — — — WDT1 WDT0 Initial value WDTMOD is a special function register to set the overflow period of the WDT counter. [Description of Bits] •...

  • Page 138: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 10 Watchdog Timer 10.3 Description of Operation The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.. The WDT counter can be cleared by writing "5AH" with the internal pointer (WDP) is "0", then writing "0A5H" with the WDP "1".
  • Page 139 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 10 Watchdog Timer Figure 10-2 shows an example of watchdog timer operation. Program Low-Speed Occurrence of Clock Start abnormality Oscillation RESET_S WDTMOD WDTMOD Setting Setting System reset Data: WDTCON Write WDTP Internal pointer Overflow WDT counter Occurrence of WDTINT WDTINT Occurrence of WDT reset...

  • Page 140: Handling Example When You Do Not Want To Use The Watch Dog Timer

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 10 Watchdog Timer 10.3.1 Handling example when you do not want to use the watch dog timer WDT counter is a free-run counter that starts count-up automatically after the system reset released and the low-speed clock (LSCLK) starts oscillating. If the WDT counter gets overflow, the WDT non-maskable interrupt occurs and then a system reset occurs.

  • Page 141: Uart

    Chapter 11 UART...

  • Page 142: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11. UART 11.1 Overview This LSI includes 1 channel of UART (Universal Asynchronous Receiver Transmitter) which is an asynchronous serial interface. For the input clock, see Chapter 6, “Clock Generation Circuit”. The use of UART requires setting of the secondary functions of Port 4. For the secondary functions of Port 4, see Chapter 15, “Port 4”.

  • Page 143: List Of Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.1.3 List of Pins Pin name Function UART0 data input pin P02/RXD0 Used for the primary function of the P02 pin. UART0 data input pin P42/RXD0* Used for the secondary function of the P42 pin. UART0 data output pin P43/TXD0 Used for the secondary function of the P43 pin.

  • Page 144: Uart0 Transmit/Receive Buffer (Ua0Buf)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.2.2 UART0 Transmit/Receive Buffer (UA0BUF) Address: 0F290H Access: R/W Access size: 8-bit Initial value: 00H UA0BUF U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 Initial value UA0BUF is a special function register (SFR) to store the transmitted/received data of the UART. In transmit mode, write transmission data to UA0BUF.

  • Page 145: Uart0 Control Register (Ua0Con)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.2.3 UART0 Control Register (UA0CON) Address: 0F291H Access: R/W Access size: 8-bit Initial value: 00H ― ― ― ― ― ― ― UA0CON U0EN Initial value UA0CON is a special function register (SFR) to start/stop communication of the UART. [Description of Bits] •...

  • Page 146: Uart0 Mode Register 0 (Ua0Mod0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.2.4 UART0 Mode Register 0 (UA0MOD0) Address: 0F292H Access: R/W Access size: 8/16 bit Initial value: 00H − − − UA0MOD0 U0RSS U0RSEL U0CK1 U0CK0 U0IO Initial value UA0MOD0 is a special function register (SFR) to set the transfer mode of the UART. [Description of Bits] •...

  • Page 147: Uart0 Mode Register 1 (Ua0Mod1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.2.5 UART0 Mode Register 1 (UA0MOD1) Address: 0F293H Access: R/W Access size: 8/16 bit Initial value: 00H − UA0MOD1 U0DIR U0NEG U0STP U0PT1 U0PT0 U0LG1 U0LG0 Initial value UA0MOD1 is a special function register (SFR) to set the transfer mode of the UART. [Description of Bits] •...
  • Page 148 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART • U0NEG (bit 5) The U0NEG bit is used to select positive logic or negative logic in the communication of the UART. U0NEG Description Positive logic (initial value) Negative logic • U0DIR (bit 6) The U0DIR bit is used to select LSB first or MSB first in the communication of the UART.

  • Page 149: Uart0 Baud Rate Registers L, H (Ua0Brtl, Ua0Brth)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.2.6 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) Address: 0F294H Access: R/W Access size: 8/16 bit Initial value: 0FFH UA0BRTL U0BR7 U0BR6 U0BR5 U0BR4 U0BR3 U0BR2 U0BR1 U0BR0 Initial value Address: 0F295H Access: R/W Access size: 8-bit Initial value: 0FH ―...

  • Page 150: Uart0 Status Register (Ua0Stat)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.2.7 UART0 Status Register (UA0STAT) Address: 0F296H Access: R/W Access size: 8-bit Initial value: 00H − − − − UA0STAT U0FUL U0PER U0OER U0FER Initial value UA0STAT is a special function register (SFR) to indicate the state of transmit or receive operation of the UART. When any data is written to UA0STAT, all the flags are initialized to “0”.
  • Page 151 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART • U0FUL (bit 3) The U0FUL bit is used to indicate the state of the transmit/receive buffer of the UART. When the transmitted data is written in UA0BUF in transmit mode, this bit is set to “1” and when this transmitted data is transferred to the shift register, this bit is set to “0”.

  • Page 152: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.3 Description of Operation 11.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can be selected as data bit.

  • Page 153: Baud Rate

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.3.2 Baud rate Baud rates are generated by the baud generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (U0CK1, U0CK0) of the UART0 mode register 0 (UA0MOD0). The count value of the baud rate generator can be set by writing it in the UART0 baud rate register H or L (UA0BRTH, UA0BRTL).

  • Page 154: Transmitted Data Direction

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.3.3 Transmitted Data Direction Figure 11-4 shows the relationship between the transmit/receive buffer and the transmitted/received data. Data length: 8 bits LSB reception LSB reception U0B2 U0B0 U0B7 U0B6 U0B5 U0B4 U0B3 U0B1 MSB reception MSB reception Data length: 7 bits LSB reception...

  • Page 155: Transmit Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.3.4 Transmit Operation Transmission is started by setting the U0IO bit of the UART0 mode register 0 (UA0MOD0) to “0” to select transmit mode and setting the U0EN bit of the UART0 control register (UA0CON) to “1”. Figure 11-5 shows the operation timing for transmission.
  • Page 156 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART Figure 11-5 Operation Timing in Transmission 11-15...

  • Page 157: Receive Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.3.5 Receive Operation Select the received data pin using the U0RSEL bit of the UART0UART0 mode register 0 (UA0MOD0). Select the receive mode by setting the U0IO bit of the UART0 mode register 0 (UA0MOD0) to "1". Then, set the U0EN bit of the UART0 control register (UA0CON) to "1"...
  • Page 158 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART Figure 11-6 Operation Timing in Reception 11-17...

  • Page 159: Detection Of Start Bit

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.3.5.1 Detection of Start Bit The Start bit is sampled using the baud rate generator clock (LSCLK, LSCLK x 2, HSCLK) selected by the U0CK1 and U0CK0 bits of the UARTn mode register 0 (UA0MOD0). Therefore, the start bit detection may be delayed for one cycle of the baud rate generate clock at the maximum.

  • Page 160: Receive Margin

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.3.5.3 Receive Margin If there is an error between the sender baud rate and the baud rate generated by the baud rate generator of this LSI, the error accumulates until the last stop bit loading in one frame, decreasing the receive margin. This receive margin needs to be fully considered, particularly when the baud rate generator clock uses a lower frequency such as LSCLK and LSCLK x 2 to realize a higher bit rate (e.g., 4800bps, 9600bps).

  • Page 161: Specifying Port Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.4 Specifying Port Registers To enable the UART function, the applicable bit of each related port register needs to be set. See Chapter 15, “Port 4” and Chapter 12, “Port 0” for detail about the port registers. 11.4.1 Functioning P43(TXD0) and P42(RXD0) as the UART Set P43MD1-P42MD1 bits(bit3-bit2 of P4MOD1 register) to “0”...

  • Page 162: Functioning P43(Txd0) And P02(Rxd0) As The Uart

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART 11.4.2 Functioning P43(TXD0) and P02(RXD0) as the UART Set P43MD1 bit (bit3 of P4MOD1 register) to “0” and set P43MD0(bit3 of P4MOD0 register) to “1”, for specifying the UART as the secondary function of P43. Register name P4MOD1 register (Address: 0F225H) P47MD1...
  • Page 163 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 11 UART The P02 pin is an input-only pin and does not need input/output selection by the register. The set value ($) is arbitrary for the P02C1 and P02C0 bits. Select an arbitrary input mode depending on the state of the external circuit to which the P02 pin is connected.

  • Page 164: Port 0

    Chapter 12 Port 0...

  • Page 165: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 12 Port 0 12. Port 0 12.1 Overview This LSI includes the 4-bit, input-only Port 0 (P00 to P03). 12.1.1 Features • All bits support a maskable interrupt function. • Allows selection of interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode, or both-edge interrupt mode for each bit.
  • Page 166 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 12 Port 0 12.2 Description of Registers 12.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F204H Port 0 data register — Depends on pin state 0F206H Port 0 control register 0 P0CON0 8/16 P0CON...

  • Page 167: Port 0 Data Register (P0D)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 12 Port 0 12.2.2 Port 0 Data Register (P0D) Address: 0F204H Access: R Access size: 8-bit Initial value: Depends on pin state ⎯ ⎯ ⎯ ⎯ P03D P02D P01D P00D Initial value P0D is a special function register (SFR) to only read the pin level of Port 0. [Description of Bits] •...

  • Page 168: Port 0 Control Registers 0, 1 (P0Con0, P0Con1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 12 Port 0 12.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) Address: 0F206H Access: R/W Access size: 8/16 bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ P0CON0 P03C0 P02C0 P01C0 P00C0 Initial value Address: 0F207H Access: R/W Access size: 8-bit Initial value: 00H...

  • Page 169: External Interrupt Control Registers 0, 1 (Exicon0, Exicon1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 12 Port 0 12.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1) Address: 0F020H Access: R/W Access size: 8-bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ EXICON0 P03E0 P02E0 P01E0 P00E0 Initial value Address: 0F021H Access: R/W Access size: 8-bit Initial value: 00H ⎯...

  • Page 170: External Interrupt Control Register 2 (Exicon2)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 12 Port 0 12.2.5 External Interrupt Control Register 2 (EXICON2) Address: 0F022H Access: R/W Access size: 8-bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ EXICON2 P03SM P02SM P01SM P00SM Initial value EXICON2 is a special function register (SFR) to select whether the Port 0 interrupt is with sampling or without sampling.

  • Page 171: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 12 Port 0 12.3 Description of Operation For each pin of Port 0, the setting of the Port 0 control registers 0 and 1 (P0CON0 and P0CON1) allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. High-impedance input mode is selected at system reset.
  • Page 172 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 12 Port 0 T16KHZ SYSCLK P0n pin P0nINT Interrupt request QP0n n = 0,1,2,3 (d) When Rising-Edge Interrupt Mode with Sampling is Selected Figure 12-2 P00 to P03 Interrupts Generation Timing 12-8...
  • Page 173 Chapter 13 Port 2...

  • Page 174: Port2

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 13 Port 2 13. Port 2 13.1 Overview This LSI includes 1-bit Port 2 (P20, P21) dedicated to output. Port 2 can output low-speed clock (LSCLK), high-speed clock (OUTCLK) as a secondary function. For the clock output, see Chapter 6, "Clock Generation Circuit."...

  • Page 175: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 13 Port 2 13.2 Description of Registers 13.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F210H Port 2 data register — 0F212H Port 2 control register 0 P2CON0 8/16 P2CON 0F213H Port 2 control register 1 P2CON1 0F214H...

  • Page 176: Port 2 Data Register (P2D)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 13 Port 2 13.2.2 Port 2 Data Register (P2D) Address: 0F210H Access: R/W Access size: 8-bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P21D P20D Initial value P2D is a special function register (SFR) to set the output value of the Port 2. The value of this register is output to Port 2. The value written to P2D is readable.

  • Page 177: Port 2 Control Registers 0, 1 (P2Con0, P2Con1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 13 Port 2 13.2.3 Port 2 Control Registers 0, 1 (P2CON0, P2CON1) Address: 0F212H Access: R/W Access size: 8/16 bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P2CON0 P21C0 P20C0 Initial value Address: 0F213H Access: R/W Access size: 8-bit Initial value: 00H...

  • Page 178: Port 2 Mode Register (P2Mod)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 13 Port 2 13.2.4 Port 2 Mode Register (P2MOD) Address: 0F214H Access: R/W Access size: 8-bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P2MOD P21MD P20MD Initial value P2MOD is a special function register (SFR) to select the primary function or the secondary function of Port 2. [Description of Bits] •...

  • Page 179: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 13 Port 2 13.3 Description of Operation 13.3.1 Output Port Function For each pin of Port 2, any one of high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, and CMOS output mode can be selected by setting the Port 2 control registers 0 and 1 (P2CON0 and P2CON1).

  • Page 180: Port 3

    Chapter 14 Port 3...

  • Page 181: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 14 Port 3 14. Port 3 14.1 Overview This LSI includes Port 3 (P35), which is a 1-bit input/output port. Furthermore, the oscillation pin (RCM) for the RC-ADC (Channel 1) are provided as the secondary function mode. For the RC-ADC, see Chapter 17, “RC Oscillation Type A/D Converter”.

  • Page 182: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 14 Port 3 14.2 Description of Registers 14.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F218H Port 3 data register — 0F219H Port 3 direction register P3DIR — 0F21AH Port 3 control register 0 P3CON0 8/16 P3CON...

  • Page 183: Port 3 Data Register (P3D)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 14 Port 3 14.2.2 Port 3 Data Register (P3D) Address: 0F218H Access: R/W Access size: 8-bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P35D Initial value P3D is a special function register (SFR) to set the value to be output to the Port 3 pin or to read the input level of the Port 3.

  • Page 184: Port 3 Direction Register (P3Dir)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 14 Port 3 14.2.3 Port 3 Direction Register (P3DIR) Address: 0F219H Access: R/W Access size: 8-bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P3DIR P35DIR Initial value P3DIR is a special function register (SFR) to select the input/output mode of Port 3. [Description of Bits] •...

  • Page 185: Port 3 Control Registers 0, 1 (P3Con0, P3Con1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 14 Port 3 14.2.4 Port 3 Control Registers 0, 1 (P3CON0, P3CON1) Address: 0F21AH Access: R/W Access size: 8/16 bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P3CON0 P35C0 Initial value Address: 0F21BH Access: R/W Access size: 8-bit Initial value: 00H...

  • Page 186: Port 3 Mode Register 0 (P3Mod0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 14 Port 3 14.2.5 Port 3 Mode Register 0 (P3MOD0) Address: 0F21CH Access: R/W Access size: 8/16 bit Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P3MOD0 P35MD0 Initial value P3MOD0 is a special function register (SFR) to select the primary function or the secondary function of Port 3. [Description of Bits] •...

  • Page 187: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 14 Port 3 14.3 Description of Operation 14.3.1 Input/Output Port Functions For each pin of Port 3, either output or input is selected by setting the Port 3 direction register (P3DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 3 control registers 0 and 1 (P3CON0 and P3CON1).

  • Page 188: Port 4

    Chapter 15 Port 4...

  • Page 189: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 15. Port 4 15.1 Overview This LSI includes Port 4 (P42 to P47) which is an 6-bit input/output port. This Port 4 can have the UART and RC-ADC output functions as the secondary and tertiary functions. For the UART, see Chapter 11, "UART."...

  • Page 190: List Of Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 15.1.3 List of Pins Pin name Primary function Secondary function P42/RXD0* Input/output port UART0 data input pin P43/TXD0 Input/output port UART0 data output pin Input/output port, RC oscillation waveform input pin for P44/ T2CK /IN1 Timer 2 external RC-ADC1 clock input...

  • Page 191: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 15.2 Description of Registers 15.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F220H Port 4 data register — 0F221H Port 4 direction register P4DIR — 0F222H Port 4 control register 0 P4CON0 8/16 P4CON...

  • Page 192: Port 4 Data Register (P4D)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 15.2.2 Port 4 Data Register (P4D) Address: 0F220H Access: R/W Access size: 8-bit Initial value: 00H ⎯ ⎯ P47D P46D P45D P44D P43D P42D Initial value P4D is a special function register (SFR) to set the value to be output to the Port 4 pin or to read the input level of the Port 4.

  • Page 193: Port 4 Direction Register (P4Dir)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 15.2.3 Port 4 Direction Register (P4DIR) Address: 0F221H Access: R/W Access size: 8-bit Initial value: 00H ⎯ ⎯ P4DIR P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR Initial value P4DIR is a special function register (SFR) to select the input/output mode of Port 4. [Description of Bits] •...

  • Page 194: Port 4 Control Registers 0, 1 (P4Con0, P4Con1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 15.2.4 Port 4 Control Registers 0, 1 (P4CON0, P4CON1) Address: 0F222H Access: R/W Access size: 8/16 bit Initial value: 00H ⎯ ⎯ P4CON0 P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 Initial value Address: 0F223H Access: R/W Access size: 8-bit Initial value: 00H...
  • Page 195 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 When output mode is selected (P45DIR When input mode is selected (P45DIR bit = Setting of P45 pin bit = “0”) “1”) P45C1 P45C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...

  • Page 196: Port 4 Mode Registers 0, 1 (P4Mod0, P4Mod1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 15.2.5 Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1) Address: 0F224H Access: R/W Access size: 8/16 bit Initial value: 00H ⎯ ⎯ P4MOD0 P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 Initial value Address: 0F225H Access: R/W Access size: 8-bit Initial value: 00H...
  • Page 197 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 • P44MD1, P44MD0 (bit 4) The P44MD1 and P44MD0 bits are used to select the primary, secondary, or tertiary function of the P44 pin. P44MD1 P44MD0 Description General-purpose input/output mode (initial value) RC oscillation waveform input pin for RC-AD (channel 1) Prohibited Prohibited •...

  • Page 198: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 15 Port 4 15.3 Description of Operation 15.3.1 Input/Output Port Functions For each pin of Port 4, either output or input is selected by setting the Port 4 direction register (P4DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 4 control registers 0 and 1 (P4CON0 and P4CON1).

  • Page 199: Port 6

    Chapter 16 Port 6...

  • Page 200: General Description

    16. Port 6 16.1 General Description ML610471/Q471 Includes Port 6 (P60 to P67) which is an 8-bit output port. ML610472/Q472 Includes Port 6 (P60 to P63) which is a 4-bit output port. ML610473/Q473 This function is not included. 16.1.1 Features •...

  • Page 201: Description Of Registers

    16.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value (*1) 0FFH 0F230H Port 6 data register — (*2) 00FH 0F232H Port 6 control register 0 P6CON0 — (*1) (*2) initial value for ML610471/ML610Q471, initial value for ML610472/ML610Q472 16-2...

  • Page 202: Port 6 Data Register (P6D)

    P6D is a special function register (SFR) to set the output value of the Port 6 pins. The value of this register is output to Port 6. The value written to P6D is readable. (*) For ML610472/ML610Q472, P67D to P64D always returns the value “0”. For ML610471/ML610Q471, the initial value of P67D to P64D is “1”.

  • Page 203: Port 6 Control Register 0 (P6Con0)

    P60C0 Initial value P6CON0 is a special function registers (SFR) to select input/output state of the Port 6 pin. For ML610472/ML610Q472, P67C0 to P64C0 always returns the value “0”. [Description of Bits] • P67C0 to P60C0 (bit 7 to 0) P67C0 to P60C0 are the bits that select either N-channel open drain output or CMOS output.

  • Page 204: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 16 Port 6 16.3 Description of Operation 16.3.1 Output Port Function For each of the Port 6 pins, N-channel open drain output mode or CMOS output mode can be selected by setting the Port 6 control register 0 (P6CON0). At the system reset, N-channel open drain output mode is selected as the initial state.

  • Page 205: Rc Oscillation Type A/D Converter

    Chapter 17 RC Oscillation Type A/D Converter...

  • Page 206: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17. RC Oscillation Type A/D Converter 17.1 Overview This LSI has a built-in 1-channel RC oscillation type A/D converter (RC-ADC). The RC-ADC converts resistance values or capacitance values to digital values by counting the oscillator clock whose frequency changes according to the resistor or capacitor connected to the RC oscillator circuits.

  • Page 207: List Of Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.1.3 List of Pins Pin name Function RC oscillation monitor pin. P35/RCM Used for the secondary function of the P35 pin. Channel 1 oscillation input pin. P44/IN1 Used for the secondary function of the P44 pin. Channel 1 reference capacitor connection pin.

  • Page 208: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.2 Description of Registers 17.2.1 List of Registers Address Name Symbol(Byte) Symbol (Word) Size Initial value 0F300H RC-ADC Counter A register 0 RADCA0 — 0F301H RC-ADC Counter A register 1 RADCA1 —...

  • Page 209: Rc-Adc Counter A Registers (Radca0-1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.2.2 RC-ADC Counter A Registers (RADCA0–1) Address: 0F300H Access: R/W Access size: 8-bit Initial value: 00H RADCA0 RAA7 RAA6 RAA5 RAA4 RAA3 RAA2 RAA1 RAA0 Initial value Address: 0F301H Access: R/W Access size: 8-bit Initial value: 00H RADCA1...

  • Page 210: Rc-Adc Counter B Registers (Radcb0-1)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.2.3 RC-ADC Counter B Registers (RADCB0–1) Address: 0F304H Access: R/W Access size: 8-bit Initial value: 00H RAB7 RAB6 RAB5 RAB4 RAB3 RAB2 RAB1 RAB0 RADCB0 Initial value Address: 0F305H Access: R/W Access size: 8-bit Initial value: 00H RAB15...

  • Page 211: Rc-Adc Mode Register (Radmod)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.2.4 RC-ADC Mode Register (RADMOD) Address: 0F308H Access: R/W Access size: 8-bit Initial value: 00H RACK2 RACK1 RACK0 RADI RADMOD Initial value RADMOD is a special function register (SFR) used to select the A/D conversion mode of the RC-ADC. [Description of Bits] •...

  • Page 212: Rc-Adc Control Register (Radcon)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.2.5 RC-ADC Control Register (RADCON) Address: 0F309H Access: R/W Access size: 8-bit Initial value: 00H RADCON RARUN — — — — — — — Initial value RADCON is a special function register (SFR) used to control A/D conversion operation of the RC-ADC. [Description of Bits] •...

  • Page 213: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.3 Description of Operation Counter A (RADCA0 and RADCA1) is a 16-bit binary counter for counting the base clock (BSCLK), which is used as the standard of time. Counter A can count up to 0FFFFH. Counter B (RADCB0 to RADCB1) is a 16-bit binary counter for counting the oscillator clock (RCCLK) of the RC oscillator circuits.
  • Page 214 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter In Table 17-1, mode No.7 is mode where external clocks to be input to the IN1 pin is used for measurement with the RC oscillator circuit stopped. As shown in Table 17-1, the oscillator circuit, RCOSC1, is so specified that they cannot operate concurrently in order to prevent interference in oscillation from occurring when they oscillate concurrently.

  • Page 215: Counter A/Counter B Reference Modes

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.3.2 Counter A/Counter B Reference Modes There are the following two modes of RC-ADC conversion operation: •Counter A reference mode (RADMOD RADI = “0”) In this mode, a gate time is determined by Counter A and the base clock (BSCLK), which is used as the time reference, then the RC oscillator clock (RCCLK) is counted by Counter B within the gate time to make the content of Counter B the A/D conversion value.
  • Page 216 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter RARUN BSCLK BSCLK RCON Overflow Counter A (+1) (+2) (+3) (10000H – nA0) 0FFFCH 0FF FEH 0FFFFH 0000H 0FFFDH Gate time nA0·t BSCLK RCCLK CR oscillator circuit Input waveform IN0/IN1 RCCLK Counter B 0000H...
  • Page 217 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter That is, “nA1” is a value inversely proportional to the RC oscillation frequency f RCCLK RARUN BSCLK BSCLK RCON Counter A 0000H nA1 – 2 nA1 – 1 nA1 – 3 0001H 0002H 0003H...

  • Page 218: Example Of Use Of Rc Oscillation Type A/D Converter

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.3.3 Example of Use of RC Oscillation Type A/D Converter This section describes the method of performing A/D conversion for sensor values in Counter A and B reference modes by taking temperature measurement by a thermistor as an example. Figure 17-5 shows the circuit configuration of 1-thermistor RC oscillator circuit using RCOSC1.
  • Page 219 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter The ratio between f (RT1) and f (RS1) is equivalent to the above-mentioned A/D conversion value nT0 that RCCLK RCCLK should ideally depend only on RT1. RCC LK Includes errors due to factors other (RT1) than RT1 Ideal...
  • Page 220 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter <First Step> <Second Step> Base clock 32.768 kHz BSCLK RADMOD (bits 4–0) RADC ON 01H (ERAD=1) 01H (ERAD=1) (bit 0) nA0·t =nB0·t (RS1) nB0·tRC CLK(RT1)=nA1·t BSCLK RCCLK BSCLK 0.366 sec CR oscillating state Oscillates with RS1...
  • Page 221 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter request is generated. (Section (a)). Also, the generation of interrupt request releases HALT mode (section (b)) and at the same time, A/D conversion operation stops. (Section (c), RARUN bit = "0"). At this time, Counter A is set to “0000H”. The content of Counter B at this time is expressed by the following expression: BSCLK nA0•...

  • Page 222: Monitoring Rc Oscillation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.3.4 Monitoring RC Oscillation The RC oscillator clock (RCCLK) can be output using the secondary function of the P35 pin of Port 3. See Chapter 14, “Port 3,” for the details of the secondary function of P35. Monitoring RC oscillation is useful for checking the characteristics of the RC oscillator circuit.

  • Page 223: Specifying Port Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter 17.4 Specifying Port Registers To enable the RC-ADC function, the applicable bit of each related port register needs to be set. See Chapter 14, “Port 3” and Chapter 15, “Port 4” for detail about the port registers. 17.4.1 Functioning P47(RT1), P46(RS1), P45(CS1) and P44(IN1) as the RC-ADC(Ch1) Set P47MD1-P44MD1 bits(bit7-bit4 of P4MOD1 register) to “0”...
  • Page 224 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 17 RC Oscillation Type A/D Converter Register P4D register (Address: 0F220H) name P43D Bit name P47D P46D P45D P44D Setting value * : Bit not related to the RC-ADC function ** : Don’t care Note: Status of output pins P45-P47 changes according to the RC oscillation mode specified by OM0-OM3 bit of RADMOD register.
  • Page 225 Chapter 18 LCD Drivers...

  • Page 226: Lcd Driver

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18. LCD Driver 18.1 Overview This LSI includes LCD drivers that display the contents that are set in the display register. For the ML610471/472/473/Q471/Q472/Q473, the numbers of commons and segments and the maximum number of dots are as shown in Table 18-1.

  • Page 227: Features

    The LCD drivers are applicable to various types of LCD panels. • ML610473/ML610Q473: 95 dots max. (19 segments x 5 commons) • ML610472/ML610Q472: 75 dots max. (15 segments x 5 commons) • ML610471/ML610Q471: 55 dots max. (11 segments x 5 commons) •...

  • Page 228: Configuration Of The Bias Generation Circuit

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.1.3 Configuration of the Bias Generation Circuit The bias generation circuit generates LCD drive voltages (V to V by multiplying the power supply voltage (V ) or the voltage (V ) generated by the voltage regulator circuit with the capacitor (C When a system reset starts the bias generation circuit operation stops.
  • Page 229 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers Bias circuit ON selected (BSON) Bias generation To LCD driver to V circuit VDD = 2.4 to 3.6V, without LCD Bias circuit ON selected (BSON) Bias generation To LCD driver to V circuit Voltage regulator circuit VDD = 1.25 to 3.6V, with LCD regulator...

  • Page 230: List Of Pins

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.1.4 List of Pins ML610471/ ML610472/ ML610473/ Pin name Input/output Function ML610Q471 ML610Q472 ML610Q473 Power supply pin for LCD bias (internally — √ √ √ generated) Power supply pin for LCD bias (internally —...

  • Page 231: Description Of Registers

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.2 Description of Registers 18.2.1 List of Registers Address Name Symbol (Byte) Symbol Initial Size (Word) value 0F0F0H Bias circuit control register BIASCON — 0F0F2H Display mode register 0 DSPMOD0 — 0F0F4H Display control register DSPCON —...

  • Page 232: Bias Circuit Control Register 0 (Biascon)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.2.2 Bias Circuit Control Register 0 (BIASCON) Address: 0F0F0H Access: R/W Access size: 8-bit Initial value: 38H BIASCON — — BSEL1 BSEL0 BSN2 BSN1 BSN0 — Initial value BIASCON is a special function register (SFR) to control the bias generation circuit. •...

  • Page 233: Display Mode Register 0 (Dspmod0)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.2.3 Display Mode Register 0 (DSPMOD0) Address: 0F0F2H Access: R/W Access size: 8/16 bit Initial value: 00H DSPMOD0 — FRM1 FRM0 — — DUTY2 DUTY1 DUTY0 Initial value DSPMOD0 is a special function register (SFR) to control the display mode of the LCD drivers. [Description of Bits] •...

  • Page 234: Display Control Register (Dspcon)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.2.4 Display Control Register (DSPCON) Address: 0F0F4H Access: R/W Access size: 8-bit Initial value: 00H DSPCON — — — — — — LMD1 LMD0 Initial value DSPCON is a special function register (SFR) to control the LCD drivers. [Description of Bits] •...

  • Page 235: Display Registers (Dspr00 To Dspr15)

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.2.5 Display Registers (DSPR00 to DSPR15) Address: 0F100H to 0F115H Access: R/W Access size: 8-bit Initial value: Undefined ⎯ ⎯ ⎯ DSPRxx Initial value DSPRxx (xx = 00 to 15H) are special function registers (SFRs) to store display data. Each valid bit of DSPRxx becomes undefined at system reset.
  • Page 236 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers Table 18-3 List of Display Registers Corresponding Register Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name segment DSPR00 0F100H SEG0 ― ― ― DSPR01 0F101H SEG1 ― ― ― DSPR02 0F102H SEG2 ―...

  • Page 237: Description Of Operation

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.3 Description of Operation 18.3.1 Operation of LCD Drivers and Bias Generation Circuit Figure 18-4 shows the operation of the LCD drivers and the bias generation circuit. Reset RESET_N Internal BIAS ON Signal LCD bias voltage Generation of LCD bias voltage ∼V...

  • Page 238: Segment Mapping When The Programmable Display Allocation Function Is Not Used

    DSPR01[3] DSPR00[3] COM3 DSPR11[2] DSPR10[2] DSPR01[2] DSPR00[2] COM2 DSPR11[1] DSPR10[1] DSPR01[1] DSPR00[1] COM1 DSPR11[0] DSPR10[0] DSPR01[0] DSPR00[0] COM0 For ML610472/Q472 DDSPR01[4] DSPR00[4] COM4 DSPR0D[4] DSPR0C[4] DSPR0D[3] DSPR0C[3] DSPR01[3] DSPR00[3] COM3 DSPR0D[2] DSPR0C[2] DSPR01[2] DSPR00[2] COM2 DSPR0D[1] DSPR0C[1] DSPR01[1] DSPR00[1] COM1...

  • Page 239: Common Output Waveforms

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.3.3 Common Output Waveforms Figure 18-6 shows the common output waveform at 1/5 duty (5 commons) and 1/3 bias. Frame frequency About 64Hz/73Hz/85Hz/102Hz COM0 COM1 COM2 COM3 COM4 Figure 18-6 Common Output Waveform at 1/5 Duty (5 Commons) and 1/3 Bias 18-14...
  • Page 240 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers Figure 18-7 shows the common output waveform at 1/5 duty (5 commons) and 1/2 bias. Frame frequency About 64Hz/73Hz/85Hz/102Hz COM0 COM1 COM2 COM3 COM4 Figure 18-7 Common Output Waveform at 1/5 Duty (5 Commons) and 1/2 Bias 18-15...

  • Page 241: Segment Output Waveform

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers 18.3.4 Segment Output Waveform Figure 18-8 shows the segment output waveform at 1/5 duty (5 commons) and 1/3 bias. Frame frequency About 64Hz/73Hz/85Hz/102Hz Data SEGn Data SEGn Data SEGn Data SEGn Data SEGn Data SEGn Data...
  • Page 242 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 18 LCD Drivers Figure 18-9 shows the segment output waveform at 1/5 duty (5 commons) and 1/2 bias. Frame frequency About 64Hz/73Hz/85Hz/102Hz Data SEGn Data SEGn Data SEGn Data SEGn Data SEGn Data SEGn Data SEGn Data SEGn Figure 18-9 Segment Output Waveform at 1/5 Duty (5 Commons) and 1/2 Bias...

  • Page 243: Power Supply Circuit

    Chapter 19 Power Supply Circuit...

  • Page 244: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 19 Power Supply Circuit 19. Power Supply Circuit 19.1 Overview This LSI includes a voltage regulator circuit for internal logic (VRL). The VRL outputs the operating voltage, V , of the internal logic circuit, program memory, RAM, low-speed oscillation, etc.

  • Page 245: Uease Flash Writer System

    Chapter 20 uEASE Flash Writer System...

  • Page 246: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 20 uEASE Flash Writer System 20. uEASE Flash Writer System 20.1 Overview This LSI(ML610Q471/Q472/Q473) has a flash memory rewrite funciton. The on-chip debug emulator (uEASE) is connected to this LSI to perform the Flash memory rewriting. 20.2 Method of Connecting to the uEASE Figure 20-1 shows connection to the uEASE.

  • Page 247: Method Of Writing To The Flash Memory

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 20 uEASE Flash Writer System 20.3 Method of writing to the Flash memory The code data size generated by the development tool is 16kByte. When you write the code data to the flash memory, you have to remove unused address region and test region. The steps explain an example of writing to the ML610Q471 flash memory.

  • Page 248: Flash Memory Rewrite Function

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 20 uEASE Flash Writer System 20.4 Flash Memory Rewrite Function Flash memory erase/write can be performed with the memory mounted on board by using the commands from the uEASE. For more details on the uEASE Flash Write System, see “FWuEASE Flash Writer Host Program User’s Manual”.

  • Page 249: Software Development

    Chapter 21 Software Development...

  • Page 250: Overview

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 21 Software Development 21. Software Development 21.1 Overview ML610Q471/ML610Q472/ML610Q472 does not have the On-chip Debug function. When developing the ML610Q471/ML610Q472/ML610Q473 software, MTP version ML610Q407 reference board is used. Because MTP version ML610Q407 has On-chip Debug function and the Mask ROM Version Emulation Funciton. The uEASE recognize ML610Q407 as ML610Q471/ML610Q472/ML610Q473 by the Mask ROM Version Emulation Funciton.

  • Page 251: Development Version Resetting Sequence

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 21 Software Development 21.3 Development Version Resetting Sequence When Development version ML610Q471/ML610Q472/ML610Q473 is returned to MTP version ML610Q407, you have to delete Development version setting file. The steps explain an example of Development version ML610Q471 resetting on ML610Q407 reference board.
  • Page 252 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 21 Software Development ●Unused address region and test region program for ML610Q472 ;--------------------------------------------------------------- Filling the Test area at code memory (for ML610472) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h DUP 0ffffh cseg at 03de8h 04720h ;Target configuration data1...

  • Page 253: Notice For The Development Version Memory Size

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 21 Software Development 21.4.2 Notice for the Development Version Memory Size The MTP version (ML610Q407) rom size is 16KB. Even if development version mode is set on MTP version, ROM size itself is 16KB physically. Therefore, do not put the program code on the unusable address region for ML610Q471/ ML610Q472/ML610Q473.

  • Page 254: The Detail Specification Of Development Version

    ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 21 Software Development 21.5 The Detail Specification of Development Version Table 21-1, 21-2 shows the difference between Development version ML610Q471/ML610Q472/ML610Q473 and ML610Q471/ML610Q472/ML610Q473. Table 21-1 Difference of function between Development version ML610Q471/472/473 and ML610Q471/472/473 Mode Development version ML610Q471 ML610Q472 ML610Q473...
  • Page 255 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 21 Software Development Table 21-2(1/3) The usable pin of ML610Q407 reference board ● : usable Δ : partial function avairable – : unusable ML610Q407 Primary/Secondary/Tertiary Function Development Version Primary function Secondary/Tertiary function Secondar ML610Q471/472/47 Pin Name Function Pin Name Function...
  • Page 256 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 21 Software Development Table 21-2 (2/3) The usable pin of ML610Q407 reference board ● : usable Δ : partial function avairable – : unusable ML610Q407 Primary/Secondary/Tertiary Function Development Version Primary Function Secondary/Tertiary Function Seconda ML610Q471/472/47 ry/Tertiar Pin Name Function Function...
  • Page 257 ML610471/472/473/Q471/Q472/Q473 User's Manual Chapter 21 Software Development Table 21-2 (3/3) The usable pin of ML610Q407 reference board ● : usable Δ : partial function avairable – : unusable ML610Q407 Primary/Secondary/Tertiary Function Development Version Pin Name Primary Function ML610Q471 ML610Q472 ML610Q473 COM0 LCD common pin ●...
  • Page 258 Appendixes...

  • Page 259: Appendix

    ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix A Registers Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value 0F000H Data segment register — 0F001H Reset status register RSTAT — Undefined 0F002H Frequency control register 0 FCON0 8/16 FCON 0F003H Frequency control register 1 FCON1 0F008H Stop code acceptor...
  • Page 260 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value 0F094H Capture time base data register CAPTB — Undefined 0F0F0H Bias circuit control register BIASCON — 0F0F2H Display mode register 0 DSPMOD0 — 0F0F4H Display control register DSPCON —...
  • Page 261 RC-ADC Counter B register 1 RADCB1 — 0F308H RC-ADC mode register RADMOD — 0F309H RC-ADC control register RADCON — (*1) ML610471/Q471 and ML610472/Q472 have this register, but ML610473/Q473 does not have it. (*2) Initial value for ML610471/Q471 (*3) Initial value for ML610472/Q472 Appendix A-3...

  • Page 262: Appendix.b Package Dimensions

    ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix B Package Dimensions Appendix B Package Dimensions 64pin TQFP Package (Unit: mm) P-TQFP64-1010-0.50-ZK9 Package material Epoxy resin Lead frame material Cu alloy Lead finish Solder thickness More than 5μm Package weight (g) 0.26typ. Rev. No./Last Revised 1 / Nov.
  • Page 263 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix B Package Dimensions 48 pin TQFP Package P-TQFP48-0707-0.50-K Package material Epoxy resin Lead frame material 42 alloy Sn-2Bi (Bi 2%typ.) Lead finish Solder thickness More than 5μm Package weight (g) 0.13typ. Rev. No./Last Revised 3 / Nov. 9,2011 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 264 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics ●Absolute Maximum Ratings = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 Ta=25°C -0.3 +4.6 Power supply voltage 2 Ta=25°C -0.3 +9.5 Power supply voltage 3 Ta=25°C -0.3 +3.6 Power supply voltage 4...
  • Page 265 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics ●Operating Conditions of Flash Memory = 0V) Parameter Symbol Condition Range Unit Operating temperature At write/erase °C At write/erase 2.75 Operating voltage At write/erase 2.75 At write/erase Rewrite count ― cycles Data retention ―...
  • Page 266 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics ●DC Characteristics (2/6) 1.25 to 3.6V, V -20 to +70°C, -40 to +85°C for P version, unless otherwise specified) =0V, Ta= Rating Measur Parameter Symbol Condition Unit ement Max. Min. Typ. circuit voltage fop=30k to 625kHz temperature ∆V...
  • Page 267 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics ●DC Characteristics for ML610471/472/473 (3/6) 3.0V, V -20 to +70°C, -40 to +85°C for P version, unless otherwise specified) =0V, Ta= Rating Measur Parameter Symbol Condition Unit ement Max. Min. Typ. circuit CPU: In STOP state. ―...
  • Page 268 IIL3 VIL3=V =1.25 to 3.6V (P42 to P47) -200 -0.01 (when pulled-up) IIH3Z VIH3=V (in high-impedance state) ― ― IIL3Z VIL3=V (in high-impedance state) ― ― : Characteristics for ML610471/Q471. : Characteristics for ML610472/Q472. : Characteristics for ML610473/Q473. Appendix C-5...

  • Page 269: Appendix.c Electrical Characteristics

    ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics ●DC Characteristics (6/6) 1.25 to 3.6V, V -20 to +70°C, -40 to +85°C for P version, unless otherwise specified) =0V, Ta= Rating Measur Parameter Symbol Condition Unit ement Min. Typ. Max. circuit Input voltage 1 (RESET_N) VIH1 ―...
  • Page 270 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics ●Measuring circuit Measuring circuit 1 32.768kHz crystal resonator : 1μF : 2.2uF : 0.1μF : 0.47μF 32.768kHz crystal resonator : DT-26 (Load capacitance 6pF) (Made by KDS:DAISHINKU CORP.) : 6pF Measuring circuit 2 (Note 2) (Note1) (Note1) Input logic circuit to determine the specified measuring conditions.
  • Page 271 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics Measuring circuit 3 (Note 2) (Note1) (Note1) Input logic circuit to determine the specified measuring conditions. (Note2) Repeats for the specified output pin Measuring circuit 4 (Note1) (Note1) Repeats for the specified input pin Measuring circuit 5 (Note1) (Note1) Input logic circuit to determine the specified measuring conditions.
  • Page 272 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics ●AC Characteristics (External Interrupt) 1.25 to 3.6V, V -20 to +70°C, -40 to +85°C for P version, unless otherwise specified) =0V, Ta= Rating Parameter Symbol Condition Unit Min. Typ. Max. Interrupt: Enabled (MIE = 1), External interrupt disable μs 76.8...
  • Page 273 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics ●AC CHARACTERISTICS (RC Oscillation A/D Converter) Condition for V =1.8 to 3.6V =1.8 to 3.6V, V =0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min.
  • Page 274 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix C Electrical Characteristics Condition for V =1.25 to 3.6V =1.25 to 3.6V, V =0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Oscillation resistor RS1,RT1 CS1≥740pF ―...
  • Page 275 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix D Application Circuit Example Appendix D Application Circuit Example SEG0 to 15 COM0 to 4 3.0V uEASE UVDD_O VTref RESET_N ML610Q473 TEST0 TEST 1kΩ RESET_N P35/RCM P44/IN1 CVR1 P45/CS1 32.768kHz P46/RT1 crystal resonator P47/RS1 Figure D-1 ML610471/472/473/Q471/Q472/Q473 Application Circuit Diagram...

  • Page 276: Appendix.e Ckeck List

    [ ] 512Byte (0:E000H to 0:E1FFH) •Unused area [ ] Please fill test area 0:1C00H0:1FFFH with BRK instruction code “0FFH” (Refer to a startup file “ML610471.asm”, “ML610472.asm”, “ML610473.asm” or programming in the source code). [ ] For fail safe in your system, please fill unused program memory area (your program code does not use) with BRK instruction code “0FFH”.
  • Page 277 ML610471/472/473/Q471/Q472/Q473 User's Manual Appendix E Check List Chapter 6 Clock Generation Circuit •Initial System clock ] At power up or system reset, the 32.768kHz crystal oscillation clock oscillates to be supplied to CPU as the system clock. •Switching high-speed clock operation mode to low-speed clock operation mode ] When switching the high-speed clock to the low-speed clock after the recovery from the STOP mode, make sure the low-speed clock is oscillating checking to see the low-speed time base counter's Q128H bit becomes "1".
  • Page 278 [ ] ML610471/ML610Q471: 3COM x 13SEG [ ] ML610471/ML610Q471: 4COM x 12SEG [ ] ML610471/ML610Q471: 5COM x 11SEG [ ] ML610472/ML610Q472: 2COM x 18SEG [ ] ML610472/ML610Q472: 3COM x 17SEG [ ] ML610472/ML610Q472: 4COM x 16SEG [ ] ML610472/ML610Q472: 5COM x 15SEG...
  • Page 279 Semiconductor development tool uEASE. [ ] Please do not apply LSIs being used for debugging to mass production. [ ] Please validate the ROM code on your production board without LAPIS Semiconductor development tool uEASE. Appendix A SFR (Specific Function Registers) •Initial value...
  • Page 280 Revision History...
  • Page 281 Final edition 1.0 FEUL610Q471-02 May 23, 2011 The package name of TQFP48 was changed. The setting of the IDEU8 was added. Add Mask ROM version FEUL610Q473-03 Sep,13, 2011 (ML610471/ML610472/ML610473) The pads number were changed. 1-15,1-16 1-15,1-16 ,1-17,1-1 ,1-17,1-1 9,1-20,1- 9,1-20,1-...

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