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ML62Q1557
LAPIS Semiconductor ML62Q1557 Manuals
Manuals and User Guides for LAPIS Semiconductor ML62Q1557. We have
1
LAPIS Semiconductor ML62Q1557 manual available for free PDF download: User Manual
LAPIS Semiconductor ML62Q1557 User Manual (882 pages)
Brand:
LAPIS Semiconductor
| Category:
Microcontrollers
| Size: 13.16 MB
Table of Contents
Table of Contents
6
Chapter 1
18
Overvier
18
Features
18
Block Diagram
33
Block Diagram of ML62Q1300 Group
33
Block Diagram of ML62Q1500 Group
34
Pin
36
Pin Layout
36
Pin List
54
Pin Description
104
Termination of Unused Pins
111
Chapter 2
112
CPU and Memory Space
112
General Description
113
CPU Nx-U16/100
115
Wait Mode and No-Wait Mode
116
Coprocessor
117
Multiplier/Divider
117
List of Coprocessor General-Purpose Registers
118
How to Use Multiplier/Divider
123
Memory Space
124
Program Memory Space
125
Data Memory Space
134
Description of Registers
148
List of Registers
148
Data Segment Register (DSR)
149
Flash Remap Address Register (REMAPADD)
150
Remapping Function
151
Description of Remapping Function
152
Software Remap
152
Code Option Remap
153
Chapter 3
154
Reset Function
154
General Description
155
Features
156
Configuration
157
List of Pins
158
Description of Registers
159
List of Registers
159
Reset Status Register (RSTAT)
160
Safety Function Reset Status Register (SRSTAT)
162
Description of Operation
163
Operation of Reset Function
163
System Reset Mode
164
Reset Input Pin Reset
164
Power-On Reset
165
Chapter 4
166
Power Management
166
General Description
167
Features
168
Configuration
169
Description of Registers
170
List of Registers
170
Stop Code Acceptor (STPACP)
171
Standby Control Register (SBYCON)
172
Software Reset Acceptor (SOFTRACP)
173
Software Reset Control Register (SOFTRCON)
174
Block Clock Control Register 0 (BCKCON0)
175
Block Clock Control Register 1 (BCKCON1)
176
Block Clock Control Register 2 (BCKCON2)
178
Block Clock Control Register 3 (BCKCON3)
180
Block Reset Control Register 0 (BRECON0)
181
Block Reset Control Register 1 (BRECON1)
182
Block Reset Control Register 2 (BRECON2)
184
Block Reset Control Register 3 (BRECON3)
186
Description of Operation
187
Program Run Mode
187
HALT Mode
187
HALT-H Mode
188
STOP Mode
189
STOP-D Mode
190
Note on Return Operation from the Standby Mode
191
Operation of each Function in Standby Mode
192
Block Control Function
194
Chapter 5
196
Interrupts
196
General Description
197
Features
197
Description of Registers
198
List of Registers
198
Interrupt Enable Register 01 (IE01)
201
Interrupt Enable Register 23 (IE23)
202
Interrupt Enable Register 45 (IE45)
204
Interrupt Enable Register 67 (IE67)
206
Interrupt Request Register 01 (IRQ01)
208
Interrupt Request Register 23 (IRQ23)
210
Interrupt Request Register 45 (IRQ45)
212
Interrupt Request Register 67 (IRQ67)
214
Interrupt Level Control Enable Register (ILEN)
216
Current Interrupt Level Management Register (CIL)
217
Interrupt Level Control Register 0 (ILC0)
218
Interrupt Level Control Register 1 (ILC1)
219
Interrupt Level Control Register 2 (ILC2)
221
Interrupt Level Control Register 3 (ILC3)
223
Interrupt Level Control Register 4 (ILC4)
225
Interrupt Level Control Register 5 (ILC5)
227
Interrupt Level Control Register 6 (ILC6)
229
Interrupt Level Control Register 7 (ILC7)
231
Description of Operation
233
Maskable Interrupt Processing
236
Non-Maskable Interrupt Processing
236
Software Interrupt Processing
236
Notes on Interrupt Routine (with Interrupt Level Control Disabled)
237
Flow Charts When Interrupt Level Control Is Enabled
243
How to Write Interrupt Processing When Interrupt Level Control Enabled
244
Interrupt Disable State
247
Chapter 6
248
Clock Generation Circuit
248
General Description
249
Features
249
Configuration
250
List of Pins
251
Description of Registers
252
List of Registers
252
High-Speed Clock Mode Register (FHCKMOD)
253
Low-Speed Clock Mode Register (FLMOD)
255
Clock Control Register (FCON)
256
High-Speed Clock Wake-Up Time Setting Register (FHWUPT)
257
Backup Control Register (FBUCON)
258
Backup Clock Status Register (FBUSTAT)
259
Clock Backup Test Mode Acceptor (FBTACP)
260
Clock Backup Test Mode (FBTCON)
261
Low-Speed RC Oscillation Frequency Adjustment Register (LRCADJ)
262
Description of Operation
263
Low-Speed Clock
263
High-Speed Clock
269
WDT Clock
270
Switching of System Clock
271
Switching Low-Speed Clock
273
Chapter 7
274
Low Speed Time Base Counter
274
General Description
275
Features
276
Configuration
277
List of Pins
279
Description of Registers
280
List of Registers
280
Low Speed Time Base Counter Register (LTBR)
281
Low Speed Time Base Register Control Register (LTBCCON)
282
Simplified RTC Time Base Counter Register (LTBRR)
283
Low Speed Time Base Counter Frequency Adjustment Register (LTBADJ)
284
Low Speed Time Base Counter Interrupt Selection Register (LTBINT)
285
Description of Operation
287
Low Speed Time Base Counter Operation
287
Low Speed Time Base Counter Frequency Adjustment Function
289
The Way of Monitoring the Frequency on LCD Drive Outputs
290
Chapter 8
292
16-Bit Timer
292
General Description
292
Features
293
Configuration
294
Description of Registers
296
List of Registers
296
16-Bit Timer N Data Register (Tmhnd: N = 0 to 7)
298
16-Bit Timer N Counter Register (Tmhnc: N = 0 to 7)
299
16-Bit Timer N Mode Register (Tmhnmod: N = 0 to 7)
300
16-Bit Timer N Interrupt Status Register (Tmhnis: N = 0 to 7)
302
16-Bit Timer N Interrupt Clear Register (Tmhnic: N = 0 to 7)
303
16-Bit Timer Start Register (TMHSTR)
304
16-Bit Timer Stop Register (TMHSTP)
306
16-Bit Timer Status Register (TMHSTAT)
308
Description of Operation
310
16-Bit Timer Mode
310
8-Bit Timer Mode
313
Common Operation
318
Chapter 9
320
Functional Timer
320
General Description
321
Features
323
Configuration
324
List of Pins
325
Description of Registers
327
List of Registers
327
Ftmn Cycle Register (Ftnp: N = 0 to 7)
332
Ftmn Event Register a (Ftnea: N = 0 to 7)
333
Ftmn Event Register B (Ftneb: N = 0 to 7)
334
Ftmn Dead Time Register (Ftndt: N = 0 to 7)
335
Ftmn Counter Register (Ftnc: N = 0 to 7)
336
Ftmn Status Register (Ftnstat: N = 0 to 7)
337
Ftmn Mode Register (Ftnmod: N = 0 to 7)
338
Ftmn Clock Register (Ftnclk: N=0 to 7)
340
Ftmn Trigger Register 0 (Ftntrg0: N = 0 to 7)
342
Ftmn Trigger Register 1 (Ftntrg1: N = 0 to 7)
345
Ftmn Interrupt Enable Register (Ftninte: N = 0 to 7)
347
Ftmn Interrupt Status Register (Ftnints: N = 0 to 7)
349
Ftmn Interrupt Clear Register (Ftnintc: N = 0 to 7)
351
FTM Common Update Register (FTCUD)
352
FTM Common Control Register (FTCCON)
353
FTM Common Start Register (FTCSTR)
354
FTM Common Stop Register (FTCSTP)
355
FTM Common Status Register (FTCSTAT)
356
Description of Operation
357
Common Sequence (Initial Setting Common to All Modes)
357
Counter Operation (Common to All Modes)
359
TIMER Mode Operation
360
CAPTURE Mode Operation
364
PWM1 Mode Operation
367
PWM2 Mode Operation
371
Event Trigger/Emergency Stop Trigger Control
375
Output at Counter Stop
378
Changing Cycle, Event A/B, and Dead Time During Operation
379
Interrupt Source
381
Chapter 10
382
Watchdog Timer
382
General Description
383
Features
384
Configuration
385
Description of Registers
386
List of Registers
386
Watchdog Timer Control Register (WDTCON)
387
Watchdog Timer Mode Register (WDTMOD)
388
Watchdog Timer Counter Register (WDTMC)
389
Watchdog Status Register (WDTSTA)
390
Description of Operation
391
How to Clear WDT Counter
392
Window Function Disabled Mode
394
Window Function Enabled Mode
398
Chapter 11
402
Serial Communication Unit
402
General Description
403
Features
404
Configuration
405
List of Pins
406
Combination of SSIO Port
410
Combination of UART Port
410
Description of Registers
411
List of Registers
411
Serial Communication Unit N Transmit/Receive Buffer (Sdnbuf)
418
Serial Communication Unit N Mode Register (Sunmod)
420
Serial Communication Unit N Transmission Interval Setting Register (Sundly)
421
Serial Communication Unit N Control Register (Suncon)
423
Synchronous Serial Port N Mode Register (Sionmod)
424
Synchronous Serial Port N Status Register (Sionstat)
426
Uartn0 Mode Register (Uan0Mod)
428
Uartn1 Mode Register (Uan1Mod)
430
Uartn0 Baud Rate Register (Uan0Brt)
432
Uartn1 Baud Rate Register (Uan1Brt)
432
Uartn0 Baud Rate Adjustment Register (Uan0Brc)
433
Uartn1 Baud Rate Adjustment Register (Uan1Brc)
433
Uartn0 Status Register (Uan0Stat)
434
Uartn1 Status Register (Uan1Stat)
436
Description of Operation
438
Synchronous Serial Port (SSIO)
438
Asynchronous Serial Interface (UART)
447
Chapter 12
457
I2C Bus Unit
457
General Description
457
Features
457
Configuration
458
Pin Setting
459
I2C Bus Unit 0 Mode Register (I2U0MSS)
461
I2C Bus 0 Receive Register (Master) (I2UM0RD)
462
I2C Bus 0 Slave Address Register (Master) (I2UM0SA)
463
I2C Bus 0 Transmit Data Register (Master) (I2UM0TD)
464
I2C Bus 0 Control Register (Master) (I2UM0CON)
465
I2C Bus 0 Mode Register (Master) (I2UM0MOD)
466
I2C Bus 0 Status Register (Master) (I2UM0STR)
468
I2C Bus 0 Receive Register (Slave) (I2US0RD)
470
I2C Bus 0 Slave Address Register (Slave) (I2US0SA)
471
I2C Bus 0 Transmit Data Register (Slave) (I2US0TD)
472
I2C Bus 0 Control Register (Slave) (I2US0CON)
473
I2C Bus 0 Mode Register (Slave) (I2US0MD)
474
I2C Bus 0 Status Register (Slave) (I2US0STA)
475
Description of Operation
477
Master Operation
477
Master Mode Communication Operation Timing
481
Slave Operation
483
Slave Mode Communication Operation Timing
487
Operation Waveforms
489
Chapter 13
492
I2C Master
492
General Description
492
Features
492
Configuration
493
List of Pins
494
Pin Setting
494
I2C Master N Slave Address Register (I2Mnsa:n=0,1)
497
I2C Master N Transmit Data Register (I2Mntd:n=0,1)
498
I2C Master N Control Register (I2Mncon:n=0,1)
499
I2C Master N Mode Register (I2Mnmod:n=0,1)
500
Description of Operation
504
Master Operation
504
Communication Operation Timing
508
Operation Waveforms
510
Chapter 14
513
DMA Controller
513
General Description
513
Features
514
Configuration
515
Description of Registers
516
List of Registers
516
DMA Channel N Transfer Mode Register (Dcnmod: N = 0, 1)
517
DMA Channel N Transfer Count Register (Dcntn: N = 0, 1)
519
DMA Channel N Transfer Source Address Register (Dcnsa: N = 0, 1)
520
DMA Channel N Transfer Destination Address Register (Dcnda: N = 0, 1)
521
DMA Transfer Enable Register (DCEN)
522
DMA Status Register (DSTAT)
523
DMA Interrupt Status Clear Register (DICLR)
524
Description of Operation
525
Procedure to Use DMA Controller
525
DMA Transfer Operation Timing Diagram
527
UART Continuous Transmission Using DMA Transfer
528
UART Continuous Reception Using DMA Transfer
529
DMA Transfer Target Block
530
Chapter 15
531
Buzzer
531
General Description
532
Features
533
Configuration
534
Description of Registers
536
List of Registers
536
Buzzer 0 Control Register (BZ0CON)
537
Buzzer 0 Mode Register (BZ0MOD)
538
Description of Operation
540
Intermittent Sound 1 Mode
540
Intermittent Sound 2 Mode
542
Single Sound Mode
543
Continuous Sound Mode
544
Common Operation
545
Chapter 16
550
Simplified RTC
550
General Description
551
Features
551
Configuration
551
Description of Registers
552
List of Registers
552
Simplified RTC Acceptor (SRTCACP)
553
Simplified RTC Minute/Second Counter (SRTCMAS)
554
Simplified RTC Control Register (SRTCCON)
556
Description of Operation
557
Simplified RTC Time Data Writing Operation
557
Simplified RTC Setting Example for Writing Time Data
558
Chapter 17
560
General Purpose Port
560
General Description
560
Features
561
Configuration
562
List of Pins
563
Description of Registers
566
List of Registers
566
Port N Data Register (Pnd:n=0 to 9, A, B)
573
Port N Mode Register 01 (Pnmod01:N=0 to 9, A, B)
574
Port N Mode Register 23 (Pnmod23:N=0 to 9, A, B)
577
Port N Mode Register 45 (Pnmod45:N=0 to 2, 4 to 9, A, B)
580
Port N Mode Register 67 (Pnmod67:N=0 to 2, 4 to 9, A, B)
583
Port N Pulse Mode Register (Pnpmd:n=0 to 3)
586
Port N Pulse Selection Register (Pnpsl:n=0 to 3)
587
PORTXT Data Input Register (PXTDI)
588
PORTXT Mode Register 01 (PXTMOD01)
589
Description of Operation
590
Input
590
Output
590
Primary Function Other than Input/Output Function
590
Shared Function
590
Carrier Frequency Output
591
Port Output Level Test
592
Port Setting Example
592
Notes for Using the P00/TEST0 Pin
593
Chapter 18
594
External Interrupt Function
594
General Description
595
Features
596
Configuration
597
External Interrupt Mode Register 0 (EIMOD0)
601
Expanded External Interrupt Control Register 0 (EEICON0)
603
Expanded External Interrupt Mode Register 0 (EEIMOD0)
604
Expanded External Interrupt Mode Register 1(EEIMOD1)
605
Expanded External Interrupt Status Register (EEISTAT)
606
Expanded External Interrupt Clear Register (EEINTC)
607
Description of Operation
608
Interrupt Request Timing
608
External Trigger Signal
609
External Interrupt Setting Flow
610
Expanded External Interrupt Setting Flow
611
Chapter 19
612
CRC (Cycle Redundancy Check) Generator
612
General Description
613
Features
614
Configuration
615
Automatic CRC Calculation Start Address Setting Register (CRCSAD)
617
Automatic CRC Calculation End Address Setting Register (CRCEAD)
618
Automatic CRC Calculation Start Segment Setting Register (CRCSSEG)
619
Automatic CRC Calculation End Segment Setting Register (CRCESEG)
620
CRC Data Register (CRCDATA)
621
CRC Calculation Result Register (CRCRES)
622
Automatic CRC Mode Register (CRCMOD)
623
Description of Operation
624
Manual CRC Calculation Mode
624
Automatic CRC Calculation Mode
630
Chapter 20
633
Analog Comparator
633
General Description
633
Features
634
Configuration
635
List of Pins
636
Description of Registers
637
List of Registers
637
Comparator N Control Register (Cmpncon: N=0,1)
638
Comparator N Mode Register (Cmpnmod: N=0,1)
639
Description of Operation
641
Analog Comparator Operation
641
Interrupt Request
642
Chapter 21
645
D/A Converter
645
Features
645
Configuration
647
List of Pins
648
Description of Registers
649
List of Registers
649
D/A Converter 0 Control Register (DACCON)
650
D/A Converter 0 Code Register (DACCODE)
651
D/A Converter 1 Control Register (DACCON1)
652
D/A Converter 1 Code Register (DACCODE1)
653
Description of Operation
654
D/A Converter Operation
654
Chapter 22
655
Voltage Level Supervisor
655
General Description
656
Features
657
Configuration
658
Description of Registers
659
List of Registers
659
Voltage Level Supervisor 0 Control Register (VLS0CON)
660
Voltage Level Supervisor 0 Mode Register (VLS0MOD)
661
Voltage Level Supervisor 0 Level Register (VLS0LV)
663
Voltage Level Supervisor 0 Sampling Register (VLS0SMP)
664
Description of Operation
665
Supervisor Mode
666
Single Mode
671
Chapter 23
676
Successive Approximation Type A/D Converter
676
General Description
677
Features
678
Configuration
679
SA-ADC Result Register N (Sadrn : N=0 to 15, 16)
684
SA-ADC Result Register (SADR)
685
SA-ADC Upper/Lower Limit Status Register 0 (SADULS0)
686
SA-ADC Upper/Lower Limit Status Register 1 (SADULS1)
687
SA-ADC Mode Register (SADMOD)
688
SA-ADC Control Register (SADCON)
689
SA-ADC Enable Register 0 (SADEN0)
690
SA-ADC Enable Register 1 (SADEN1)
691
SA-ADC Conversion Interval Setting Register (SADSTM)
692
SA-ADC Upper/Lower Limit Mode Register (SADLMOD)
693
SA-ADC Upper Limit Setting Register (SADUPL)
694
SA-ADC Lower Limit Setting Register (SADLOL)
694
SA-ADC Reference Voltage Control Register (VREFCON)
695
SA-ADC Interrupt Mode Register (SADIMOD)
696
SA-ADC Trigger Register (SADTRG)
697
SA-ADC Test Mode Register (SADTMOD)
698
Description of Operation
699
Operation of Successive Approximation Type A/D Converter
699
How to Test the Successive Approximation Type A/D Converter
703
A/D Conversion Time Setting
704
Notes on SA-ADC
707
Sampling Time Setting
707
Noise Suppression
708
Chapter 24 Regulator
710
General Description
710
Features
711
Configuration
712
List of Pins
713
Description of Operation
713
Chapter 25
715
Flash Memory
715
General Description
715
List of Pins
718
Description of Registers
719
List of Registers
719
Flash Address Register (FLASHA)
720
Flash Segment Register (FLASHSEG)
721
Flash Data Register 0 (FLASHD0)
723
Flash Data Register 1 (FLASHD1)
724
Flash Control Register (FLASHCON)
725
Flash Acceptor (FLASHACP)
726
Flash Self Register (FLASHSLF)
727
Flash Status Register (FLASHSTA)
728
Self-Programming
729
Programming Program Memory Space
730
Programming Data Flash Area
732
Notes on Use of Self-Programming
734
In-System Programming Function
735
Programming Procedure
735
Communication Method
735
Communication Command
736
Transition Command to ISP Mode
737
Flash Memory Handling
738
Chapter 26
744
Code Option
744
General Description
744
Function List
744
Description of Code Option
745
Code Options 0 (CODEOP0)
745
Code Options 1 (CODEOP1)
746
Code Options 2 (CODEOP2)
747
Code Option Data Setting
748
Chapter 27
751
LCD Driver
751
General Description
751
Features
751
Configuration of LCD Display Function
752
Configuration of Bias Generation Circuit
753
List of Pins
755
Description of Registers
758
List of Registers
758
Bias Control Register(BIASCON)
759
Display Mode Register(DSPMOD)
761
Display Control Register(DSPCON)
762
Segment Mode Register0 (SEGMOD0)
763
Segment Mode Register1 (SEGMOD1)
765
Segment Mode Register2 (SEGMOD2)
767
Segment Mode Register3 (SEGMOD3)
769
Segment Mode Register4 (SEGMOD4)
771
Display Register(DSPR00 to DSPR64)
772
Description of Operation
775
Display Register Segment Map
775
Common Output Waveform
776
Segment Output Waveform
778
Common Output Waveform for LED Drive
782
Segment Output Waveform for LED Drive
784
Chapter 28
788
On-Chip Debug Function
788
General Description
789
Features
790
Configuration
791
List of Pins
792
How to Use On-Chip Debug Function
793
Precautions
793
Operation of Peripheral Circuits During Breaks in the On-Chip Debug Mode
794
Chapter 29
796
Safety Function
796
General Description
796
Features
797
Description of Registers
798
List of Registers
798
RAM Guard Setting Register (RAMGD)
799
SFR Guard Setting Register 0 (SFRGD0)
800
SFR Guard Setting Register 1 (SFRGD1)
801
RAM Parity Setting Register (RASFMOD)
803
Communication Test Setting Register (COMFT0)
804
MCU Status Interrupt Enable Register (MCINTEL)
805
MCU Status Interrupt Register (MCISTATL)
806
MCU Status Interrupt Clear Register (MCINTCL)
807
Description of Operation
808
Communication Function Self-Test
808
Unused ROM Area Access Reset Function
809
Clock Mutual Monitoring Function
810
CRC Calculation
812
WDT Counter Read
812
Port Output Level Test
812
Successive Approximation Type A/D Converter Test
812
Clock Backup Function and Its Test
812
Appendix A Register List
814
Appendix B Package Dimensions
838
Appendix C Instruction Execution Cycle
851
Appendix D Application Circuit Example
859
Appendix E List of Notes
860
Revision History
881
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