LAPIS Semiconductor ML62Q1000 Series User Manual page 675

Figure 22-11 shows an example of the operation timing diagram with sampling in single mode 2.
VLS0EN bit
VLS0RF
Threshold voltage
V
VLS0 comparator
comparison result
Sampling clock
VLS0F
VLS0 interrupt
The operation shown in Figure 22-11 is described below:
(1) Choose a detection voltage by the VLS0LV3 to VLS0LV0 bits of the VLS0LV register.
(2) Choose "Sampling with HSCLK" or "Sampling with LSCLK" by the VLS0SM1 and VLS0SM0 bits of the
VLS0SMP register.
(3) Write "0x01" to VLS0AMD[1:0] bits of VLS0MOD register in order to choose the single mode 2.
(4) Choose an operation function by the VLS0SEL1 and VLS0SEL0 bits of the VLS0MOD register.
(5) Write "1" to the VLS0EN bit to enable VLS0 operation.
(6) Wait until the comparison result of the VLS0 comparator is stabilized.
(7) If V
is below the threshold voltage (V
DD
and the VLS0 interrupt (low voltage) is generated. If V
VLS0F bit is cleared to "0" and the VLS0 interrupt (low voltage) is not generated.
(8) After the interrupt is generated, the VLS0EN bit is set to "0" and VLS0 is disabled again.
[Note]
Ÿ
Entering the STOP/STOP-D mode is not allowed while the single mode operation is in progress. Enter
the STOP/STOP-D mode after the single mode operation is completed (VLS0EN bit="0").
Ÿ
If VDD is higher than the specified threshold voltage, the VLS0 interrupt is not generated.
FEUL62Q1000
(1)~(5)
↓
DD
Stabilization
time
Figure 22-11 Operation Timing Diagram with Sampling (Single Mode 2)
VLSF
(6) (7) (8)
↓ ↓
↓
) after three cycles of the sampling clock, the VLS0F bit is set to "1"
is equal to or above the threshold voltage (V
DD
ML62Q1000 Series User's Manual
Chapter 22 Voltage Level Supervisor
V
VLSF
V
SS
), the
VLSF
22-20