LAPIS Semiconductor ML62Q1000 Series User Manual page 395

The following figure shows an operation timing overview of the window function disabled mode
Overflow period (T
Figure 10-6
The following table shows the WDT counter clear enabled period in the window function disabled mode.
Table 10-3 WDT Counter Clear Enabled Period in Window Function Disabled Mode
WDT2 WDT1
0
0
0
0
1
1
1
1
*1: Time when the WDTCLK is 1 .024kHz. If choosing RC1K oscillation for the WDTCLK, the frequency has a
significant error.
The clear processing is enable for two clocks of the WDTCLK (2ms when the WDTCLK is
*2:
1.024kHz) before the WDT gets overflowed.
FEUL62Q1000
WDT counter value
)
WOV
0
WDT interrupt generated
Overflow period
(T
WOV
Overview of Operation Timing in Window Function Disabled Mode
Overflow
WDT0
period
(T )
WOV
7.8 ms
0 0
15.6 ms
0 1
31.3 ms
1 0
62.5 ms
1 1
125 ms
0 0
500 ms
0 1
2000 ms
1 0
8000 ms
1 1
Clear enabled period (T
WCL
Overflow period
) (T
WOV
WDT reset generation time
WDT reset
WDT counter clear enabled period
generation
*1 *1
time
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
1000 ms
4000 ms
16000 ms
ML62Q1000 Series User's Manual
Chapter 10 Watchdog Timer
Time
WDT cleared
)
)
*1*2
(T )
WCL
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ Overflow period
10-13