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LAPIS Semiconductor ML62Q1000 Series User Manual

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Table of Contents

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FEUL62Q1000-01
ML62Q1000 Series
ML62Q1300 Group
ML62Q1500 Group
ML62Q1700 Group
User's Manual
Issue Date: Dec 11, 2018

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Summary of Contents for LAPIS Semiconductor ML62Q1000 Series

  • Page 1 FEUL62Q1000-01 ML62Q1000 Series ML62Q1300 Group ML62Q1500 Group ML62Q1700 Group User's Manual Issue Date: Dec 11, 2018...
  • Page 2 Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information.
  • Page 3 ML62Q1000 Series User's Manual Notes for product usage Notes on this page are applicable to the all microcontroller devices. For individual notes on each product, refer to [Note] in the chapters of each user's manual. The description contents on this page take priority over those in the chapters if they are different.
  • Page 4 ML62Q1000 Series User's Manual Preface This manual describes the operation of the hardware of the 16-bit microcontroller ML62Q1000 Series. This manual is for ML62Q1300 group, ML62Q1500 group and ML62Q1700 group. See other manuals for ML62Q1200 group, ML62Q1400 group and ML62Q1600 group.
  • Page 5 ML62Q1000 Series User's Manual Notation Classification Notation Description ¨ Numeric value XXh, XXH, 0xXX Indicates a hexadecimal number. ¨ Unit word, W 1 word = 16 bits byte, B 1 byte = 8 bits nibble, N 1 nibble = 4 bits...

  • Page 6: Table Of Contents

    ML62Q1000 Series User's Manual Contents Table of Contents Chapter 1 Overvier ................................1-1 1.1 Features ................................1-1 1.2 BLOCK DIAGRAM ............................. 1-16 1.2.1 Block Diagram of ML62Q1300 Group....................... 1-16 1.2.2 Block Diagram of ML62Q1500 Group....................... 1-16 1.2.3 Block Diagram of ML62Q1700 Group....................... 1-16 1.3 PIN ................................
  • Page 7 ML62Q1000 Series User's Manual Contents Chapter 4 Power Management ............................4-1 4.1 General Description ............................4-1 4.1.1 Features ................................4-2 4.1.2 Configuration ..............................4-3 4.2 Description of Registers..........................4-4 4.2.1 List of Registers ............................. 4-4 4.2.2 Stop Code Acceptor (STPACP) ........................4-5 4.2.3 Standby Control Register (SBYCON) ......................
  • Page 8 ML62Q1000 Series User's Manual Contents 5.3.4 Notes on Interrupt Routine (with Interrupt Level Control Disabled) ............5-41 5.3.5 Flow Charts When Interrupt Level Control Is Enabled ................5-46 5.3.6 How To Write Interrupt Processing When Interrupt Level Control Enabled ..........5-48 5.3.7 Interrupt Disable State ..........................
  • Page 9 ML62Q1000 Series User's Manual Contents 8.2.4 16-Bit Timer n Mode Register (TMHnMOD: n = 0 to 7) ................8-9 8.2.5 16-Bit Timer n Interrupt Status Register (TMHnIS: n = 0 to 7) ..............8-11 8.2.6 16-Bit Timer n Interrupt Clear Register (TMHnIC: n = 0 to 7) ..............8-12 8.2.7 16-Bit Timer Start Register (TMHSTR) .....................
  • Page 10 ML62Q1000 Series User's Manual Contents 10.2.3 Watchdog Timer Mode Register (WDTMOD) ..................10-6 10.2.4 Watchdog Timer Counter Register (WDTMC) ..................10-7 10.2.5 Watchdog Status Register (WDTSTA) ...................... 10-8 10.3 Description of Operation ........................... 10-9 10.3.1 How to Clear WDT Counter ........................10-10 10.3.2 Window Function Disabled Mode ......................
  • Page 11 ML62Q1000 Series User's Manual Contents 12.2.14 I2C Bus 0 Status Register (Slave) (I2US0STA) ..................12-19 12.3 Description of Operation ......................... 12-21 12.3.1 Master Operation ............................. 12-21 12.3.2 Master Mode Communication Operation Timing ..................12-25 12.3.3 Slave Operation ............................12-27 12.3.4 Slave Mode Communication Operation Timing ..................12-31 12.3.5 Operation Waveforms ..........................
  • Page 12 ML62Q1000 Series User's Manual Contents 15.2.2 Buzzer 0 Control Register (BZ0CON)....................... 15-6 15.2.3 Buzzer 0 Mode Register (BZ0MOD) ......................15-7 15.3 Description of Operation ........................... 15-9 15.3.1 Intermittent Sound 1 Mode ........................15-9 15.3.2 Intermittent Sound 2 Mode ........................15-11 15.3.3 Single Sound Mode ..........................
  • Page 13 ML62Q1000 Series User's Manual Contents 18.2.1 List of Registers ............................18-6 18.2.2 External Interrupt Control Register 0 (EICON0) ..................18-7 18.2.3 External Interrupt Mode Register 0 (EIMOD0) ..................18-8 18.2.4 Expanded External Interrupt Control Register 0 (EEICON0) ..............18-10 18.2.5 Expanded External Interrupt Mode Register 0 (EEIMOD0) ..............18-11 18.2.6 Expanded External Interrupt Mode Register 1(EEIMOD1) ..............
  • Page 14 ML62Q1000 Series User's Manual Contents 21.2.5 D/A Converter 1 Code Register (DACCODE1) ..................21-9 21.3 Description of Operation ......................... 21-10 21.3.1 D/A Converter Operation ......................... 21-10 Chapter 22 22. Voltage Level Supervisor ..........................22-1 22.1 General Description ........................... 22-1 22.1.1 Features ..............................22-2 22.1.2 Configuration .............................
  • Page 15 ML62Q1000 Series User's Manual Contents 24.2 Description of Operation ........................24-2 Chapter 25 25. Flash Memory .............................. 25-1 25.1 General Description ........................... 25-1 25.1.1 List of Pins ..............................25-4 25.2 Description of Registers ..........................25-5 25.2.1 List of Registers ............................25-5 25.2.2 Flash Address Register (FLASHA) ......................
  • Page 16 ML62Q1000 Series User's Manual Contents 27.3.1 Operation of LCD Driver Circuit LCDs ....................27-25 27.3.2 Display Register Segment Map ....................... 27-25 27.3.3 Common Output Waveform ........................27-26 27.3.4 Segment Output Waveform ........................27-28 27.3.5 Common Output Waveform for LED drive ..................... 27-32 27.3.6 Segment Output Waveform for LED drive ....................
  • Page 17 Chapter 1 Overview...

  • Page 18: Overvier

    Chapter 1 Overview Overview 1.1 Features ML62Q1000 Series is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with program memory(Flash memory* ), data memory(RAM), data Flash and rich peripheral functions such as the multiplier/divider, CRC operator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports,...
  • Page 19 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-3 ML62Q1700 Group Product List 100pin 64pin Program Data 80pin Data 48pin 52pin QFP64 QFP100 Flash TQFP48 TQFP52 memory memory QFP80 TQFP64 TQFP100 256Kbyte ML62Q1727 ML62Q1737 ML62Q1747 192Kbyte 16Kbyte ML62Q1726 ML62Q1736 ML62Q1746 160Kbyte ML62Q1725 ML62Q1735...
  • Page 20 ML62Q1000 Group User's Manual Chapter 1 Overview − 16-bit RISC CPU (CPU name: nX-U16/100) − Instruction system: 16-bit length instruction − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on −...
  • Page 21 ML62Q1000 Group User's Manual Chapter 1 Overview Reset − RESET_N pin reset − Reset by power-on detection − Reset by the 2 watchdog timer (WDT) overflow − Reset by WDT counter clear during the clear invalid period − Reset by RAM parity error −...
  • Page 22 ML62Q1000 Group User's Manual Chapter 1 Overview l Simplified RTC (ML62Q1500 and ML62Q1700 group) − Channel: 1 ch − Count by one second from "00 min. 00 sec" to "59 min. 59 sec" − One interrupt occurrence is selectable from four periodical interrupt requests (0.5sec, 1sec, 30sec or 60sec) −...
  • Page 23 ML62Q1000 Group User's Manual Chapter 1 Overview C bus interface unit (Master / Slave) − Channel: 1ch − Master or Slave mode is selectable < Master function > ‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s) ‒...
  • Page 24 ML62Q1000 Group User's Manual Chapter 1 Overview Buzzer − 4 buzzer mode (Repeat sound, Single sound, Intermittent sound 1 and Intermittent sound 2) − 8frequencies (4.096kHz to 293Hz) − 15 step duty (1/16 to 15/16) − Slectable initial level (L or H) CRC(Cycle Redundancy Check) operation function −...
  • Page 25 ML62Q1000 Group User's Manual Chapter 1 Overview Shipping pacakge ML62Q1300 group − 16-pin plastic SSOP ML62Q1323/1324/1325-xxxMB (Blank part: ML62Q1323/1324/1325-NNNMB) − 16-pin plastic WQFN ML62Q1323/1324/1325-xxxGD (Blank part: ML62Q1323/1324/1325-NNNGD) − 20-pin plastic TSSOP ML62Q1333/1334/1335-xxxTD (Blank part: ML62Q1333/1334/1335-NNNTD) − 24-pin plastic WQFN ML62Q1345/1346/1347-xxxGD (Blank part: ML62Q1345/1346/1347-NNNGD) −...
  • Page 26 :Custom Code Number Program Memory Size :16Kbyte :24Kbyte :32Kbyte :48Kbyte :64Kbyte Pin Count :16pin :20pin :24pin :32pin Group Name :1300 Group Program Memory Type :Flash Memory CPU Type :16bit CPU nX-U16/100 LAPIS Semiconductor Logic Product Figure 1-1 ML62Q1300 Group Part Number FEUL62Q1000...
  • Page 27 : 52 pin : 64 pin : 80 pin : 100 pin Group number : 1500 group Program Memory Type : Flash Memory CPU Type : 16 but CPU nX-U16/100 LAPIS Semiconductor Logic Product Figure 1-2 ML62Q1500 Group Part Number FEUL62Q1000 1-10...
  • Page 28 : 52 pin : 64 pin : 80 pin : 100 pin Group number : 1700 group Program Memory Type : Flash Memory CPU Type : 16 bit CPU nX-U16/100 LAPIS Semiconductor Logic Product Figure 1-3 ML62Q1700 Group Part Number FEUL62Q1000 1-11...
  • Page 29 ML62Q1000 Group User's Manual Chapter 1 Overview ML62Q1300 Group Main Function List Table 1-4 Main Function List Interrupt Timer Serial Analog Part number ML62Q1323 ML62Q1324 ML62Q1325 ML62Q1333 ML62Q1334 ML62Q1335 ML62Q1345 ML62Q1346 ML62Q1347 ML62Q1365 ML62Q1366 ML62Q1367 : One 16bit timer is configurable as two 8bit timers : Full-duplex UART and Synchronous Serial Port are unavailable to use simultaneously in the same channel.
  • Page 30 ML62Q1000 Group User's Manual Chapter 1 Overview ML62Q1500 Group Main Function List Table 1-5 Main Function List Interrupt Timer Serial Analog Part number ML62Q1530 ML62Q1531 ML62Q1532 ML62Q1533 ML62Q1534 ML62Q1540 ML62Q1541 ML62Q1542 ML62Q1543 ML62Q1544 ML62Q1550 ML62Q1551 ML62Q1552 ML62Q1553 ML62Q1554 ML62Q1555 ML62Q1556 ML62Q1557 ML62Q1563 ML62Q1564...
  • Page 31 ML62Q1000 Group User's Manual Chapter 1 Overview ML62Q1700 Group Main Function List Table 1-6 Main Function List Interrupt Timer Serial Analog Part number ML62Q1700 ML62Q1701 ML62Q1702 ML62Q1703 ML62Q1704 ML62Q1710 ML62Q1711 ML62Q1712 ML62Q1713 ML62Q1714 ML62Q1720 ML62Q1721 ML62Q1722 ML62Q1723 ML62Q1724 ML62Q1725 ML62Q1726 ML62Q1727 ML62Q1733 ML62Q1734...
  • Page 32 ML62Q1000 Group User's Manual Chapter 1 Overview : Shared with pins for crystal oscillation : The LCD common/segment shared pins are shared for common or segment, selectable by setting a SFR : All LCD drive pins are shared with general purpose I/O ports. FEUL62Q1000 1-15...

  • Page 33: Block Diagram

    ML62Q1000 Group User's Manual Chapter 1 Overview 1.2 BLOCK DIAGRAM 1.2.1 ML62Q1300 Group Block Diagram of CPU (nX-U16/100) ECSR1-3 EPSW1-3 ELR1-3 Multiplier/Divider GREG (Coprocessor) 0 - 15 DSR/CSR Timing Controller Program memory (Flash) Controller Instruction Instruction On-Chip Decoder Register SU0-1_SCLK* SU0-1_SIN* SU0-1_SOUT* Power...

  • Page 34: Block Diagram Of Ml62Q1500 Group

    ML62Q1000 Group User's Manual Chapter 1 Overview 1.2.2 ML62Q1500 Group Block Diagram of CPU (nX-U16/100) ECSR1-3 EPSW1-3 ELR1-3 Multiplier/Divider GREG (Coprocessor) 0 -15 DSR/CSR Timing Controller Program memory (Flash) Controller Instruction Instruction On-Chip Decoder Register SU0-5_SCLK* SU0-5_SIN* SU0-5_SOUT* Power Serial Circuit Unit SU0-5_RXD0*...
  • Page 35 ML62Q1000 Group User's Manual Chapter 1 Overview 1.2.3 ML62Q1700 Group Block Diagram of CPU (nX-U16/100) ECSR1-3 EPSW1-3 ELR1-3 Multiplier/Divider GREG (Coprocessor) 0 -15 DSR/CSR Timing Controller Program memory (Flash) Controller Instruction Instruction On-Chip Decoder Register SU0-5_SCLK* SU0-5_SIN* SU0-5_SOUT* Power Serial Circuit Unit SU0-5_RXD0*...

  • Page 36: Pin

    ML62Q1000 Group User's Manual Chapter 1 Overview 1.3 PIN 1.3.1 Pin Layout 1.3.1.1 ML62Q1323/1324/1325 16pin SSOP P27/EXI7/EXTRG7 P26/EXI6/EXTRG6 P23/EXI5/EXTRG5 RESET_N (TOP VIEW) SSOP16 P21/EXI4/EXTRG4 P00/TEST0 P02/EXI0/EXTRG0 P17/EXI3/EXTRG3 P03/EXI1/EXTRG1 P04/EXI2/EXTRG2 Figure 1-7 Pin Layout of ML62Q1323/1324/1325 16pin SSOP FEUL62Q1000 1-19...
  • Page 37 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.2 ML62Q1323/1324/1325 16pin WQFN P23/EXI5/EXTRG5 P04/EXI2/EXTRG2 P26/EXI6/EXTRG6 (TOP VIEW) WQFN16 P03/EXI1/EXTRG1 P27/EXI7/EXTRG7 P02/EXI0/EXTRG0 Figure 1-8 Pin Layout of ML62Q1323/1324/1325 16pin WQFN FEUL62Q1000 1-20...
  • Page 38 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.3 ML62Q1333/1334/1335 20pin TSSOP RESET_N P00/TEST0 P02/EXI0/EXTRG0 P03/EXI1/EXTRG1 P27/EXI7/EXTRG7 P04/EXI2/EXTRG2 (TOP VIEW) TSSOP20 P26/EXI6/EXTRG6 P17/EXI3/EXTRG3 P23/EXI5/EXTRG5 P21/EXI4/EXTRG4 Figure 1-9 Pin Layout of ML62Q1333/1334/1335 20pin TSSOP FEUL62Q1000 1-21...
  • Page 39 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.4 ML62Q1345/1346/1347 24pin WQFN P26/EXI6/EXTRG6 (TOP VIEW) WQFN24 P27/EXI7/EXTRG7 P04/EXI2/EXTRG2 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 Figure 1-10 Pin Layout of 1345/1346/1347 24pin WQFN FEUL62Q1000 1-22...
  • Page 40 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.5 ML62Q1365/1366/1367 32pin TQFP P26/EXI6/EXTRG6 P27/EXI7/EXTRG7 (TOP VIEW) TQFP32 P04/EXI2/EXTRG2 Figure 1-11 Pin Layout of ML62Q1365/1366/1367 32pin TQFP FEUL62Q1000 1-23...
  • Page 41 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.6 ML62Q1365/1366/1367 32pin WQFN P26/EXI6/EXTRG6 P27/EXI7/EXTRG7 (TOP VIEW) WQFN32 P04/EXI2/EXTRG2 Figure 1-12 Pin Layout of ML62Q1365/1366/1367 32pin WQFN FEUL62Q1000 1-24...
  • Page 42 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.7 ML62Q1530/1531/1532/1533/1534 48pin TQFP Figure 1-13 ML62Q1530/1531/1532/1533/1534 48pin TQFP FEUL62Q1000 1-25...
  • Page 43 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.8 ML62Q1540/1541/1542/1543/1544 52pin TQFP Figure 1-14 ML62Q1540/1541/1542/1543/1544 52pin TQFP FEUL62Q1000 1-26...
  • Page 44 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.9 ML62Q1550/1551/1552/1553/1554/1555/1556/1557 64pin TQFP/QFP Figure 1-15 ML62Q1550/1551/1552/1553/1554/1555/1556/1557 64pin TQFP/QFP FEUL62Q1000 1-27...
  • Page 45 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.10 ML62Q1563/1564/1565/1566/1567 80pin QFP P50/EXI8 TOP VIEW QFP80 P64/EXI9 P04/EXI2/EXTRG2 Figure 1-16 ML62Q1563/1564/1565/1566/1567 80pin TQFP/QFP FEUL62Q1000 1-28...
  • Page 46 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.11 ML62Q1573/1574/1575/1576/1577 100pin TQFP TOP VIEW P50/EXI8 TQFP100 P64/EXI9 P04/EXI2/EXTRG2 Figure 1-17 ML62Q1573/1574/1575/1576/1577 100pin TQFP FEUL62Q1000 1-29...
  • Page 47 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.12 ML62Q1573/1574/1575/1576/1577 100pin QFP TOP VIEW QFP100 P50/EXI8 P64/EXI9 P04/EXI2/EXTRG2 Figure 1-18 ML62Q1573/1574/1575/1576/1577 100pin QFP FEUL62Q1000 1-30...
  • Page 48 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.13 ML62Q1700/1701/1702/1703/1704 48pin TQFP Figure 1-19 ML62Q1700/1701/1702/1703/1704 48pin TQFP FEUL62Q1000 1-31...
  • Page 49 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.14 ML62Q1710/1711/1712/1713/1714 52pin TQFP Figure 1-20 ML62Q1710/1711/1712/1713/1714 52pin TQFP FEUL62Q1000 1-32...
  • Page 50 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.15 ML62Q1720/1721/1722/1723/1724/1725/1726/1727 64pin TQFP/QFP TOP VIEW QFP64 /TQFP64 Figure 1-21 ML62Q1720/1721/1722/1723/1724/1725/1726/1727 64pin TQFP/QFP FEUL62Q1000 1-33...
  • Page 51 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.16 ML62Q1733/1734/1735/1736/1737 80pin QFP PB2/SEG43 P96/SEG15 PB3/SEG44 P95/SEG14 PB4/SEG45 P94/SEG13 PB5/SEG46 P93/SEG12 P40/SEG47 P53/SEG8 P41/SEG48 P52/SEG7 P30/SEG49 P51/SEG6 P31/SEG50 P50/EXI8/SEG5 P32/SEG51 P13/COM7/SEG4 TOP VIEW P33/SEG52 P12/COM6/SEG3 QFP80 P60/SEG53 P11/COM5/SEG2 P61/SEG54 P10/COM4/SEG1 P62/SEG55 P07/COM3/SEG0 P63/SEG56 P06/COM2 P64/EXI9/SEG57...
  • Page 52 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.17 ML62Q1743/1744/1745/1746/1747 100pin TQFP PB0/SEG41 PA0/SEG17 PB1/SEG42 P97/SEG16 PB2/SEG43 P96/SEG15 PB3/SEG44 P95/SEG14 PB4/SEG45 P94/SEG13 PB5/SEG46 P93/SEG12 P40/SEG47 P92/SEG11 P41/SEG48 P91/SEG10 P30/SEG49 P90/SEG9 P31/SEG50 P53/SEG8 P32/SEG51 P52/SEG7 P33/SEG52 P51/SEG6 TOP VIEW P60/SEG53 P50/EXI8/SEG5 TQFP100 P61/SEG54 P13/COM7/SEG4 P62/SEG55...
  • Page 53 ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.1.18 ML62Q1743/1744/1745/1746/1747 100pin QFP PB3/SEG44 P96/SEG15 PB4/SEG45 P95/SEG14 PB5/SEG46 P94/SEG13 P40/SEG47 P93/SEG12 P41/SEG48 P92/SEG11 P30/SEG49 P91/SEG10 P31/SEG50 P90/SEG9 P32/SEG51 P53/SEG8 P33/SEG52 P52/SEG7 TOP VIEW P60/SEG53 P51/SEG6 QFP100 P61/SEG54 P50/EXI8/SEG5 P62/SEG55 P13/COM7/SEG4 P63/SEG56 P12/COM6/SEG3 P64/EXI9/SEG57 P11/COM5/SEG2 P65/SEG58...

  • Page 54: Pin List

    ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.2 PIN LIST Table 1-7 shows the pin lists of ML62Q1300 group. "(I)" indicates the input pin and "(I/O)" indicates the input/output pin. Table 1-7 ML62Q1300 Group Pin List (1/5) Pn name Primary function Shared function −...
  • Page 55 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-7 ML62Q1300 Group Pin List (2/5) Pn name Primary function Shared function − function − function function I2CM0_SDA − function General I/O pin （I/O） − function − function − function function SU0_RXD1 function SU0_RXD0 function...
  • Page 56 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-7 ML62Q1300 Group Pin List (3/5) Pn name Primary function Shared function − function − function function I2CU0_SDA − function General I/O pin （I/O） − function − function − function function SU1_SCLK −...
  • Page 57 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-7 ML62Q1300 Group Pin List (4/5) Pn name Primary function Shared function function SU1_RXD0/SU1_SIN − function − function − General I/O pin function （I/O） − function − function function AIN4 function SU1_TXD0/SU1_SOUT function SU1_TXD1 −...
  • Page 58 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-7 ML62Q1300 Group Pin List (5/5) Pn name Primary function Shared function function SU1_RXD1 function SU1_RXD0 − function − function General I/O pin （I/O） − function − function − function function SU1_TXD1 −...
  • Page 59 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 shows the pin lists of ML62Q1500 group. "(I)" indicates the input pin and "(I/O)" indicates the input/output pin. Table 1-8 ML62Q1500 Group Pin List (1/23) ML62Q1500 group Pn name Primary function Shared function Positive power pin 42 52 54...
  • Page 60 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (2/23) ML62Q1500 group Pn name Primary function Shared function function SU0_SCLK function P04 / General I/O pin functiion I2CU0_SCL EXI2 External interrupt 2 16 17 21 25 30 32 function TMH0OUT /EXTRG2...
  • Page 61 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (3/23) ML62Q1500 group Pn name Primary function Shared function function SU0_TXD1 function functiion 20 21 25 29 34 36 General I/O pin function (I/O) function function function function SU0_SCLK function...
  • Page 62 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (4/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 25 27 35 45 57 59 General I/O pin function (I/O) function function function function function functiion I2CU0_SDA...
  • Page 63 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (5/23) ML62Q1500 group Pn name Primary function Shared function function SU0_TXD1 function functiion 29 31 39 49 61 63 General I/O pin function FTM1N (I/O) function TBCOUT1 function BZ0N function...
  • Page 64 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (6/23) ML62Q1500 group Pn name Primary function Shared function function SU1_RXD0/SU1_SIN function functiion 33 35 43 53 65 67 General I/O pin function (I/O) function function function AIN4 function SU1_TXD0/SU1_SOUT...
  • Page 65 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (7/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 37 41 51 67 84 86 General I/O pin function (I/O) function function function function function functiion 38 42 52 68 85 87...
  • Page 66 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (8/23) ML62Q1500 group Pn name Primary function Shared function function SU5_TXD1 function functiion 49 65 General I/O pin function (I/O) function function function function function functiion 40 50 66 General I/O pin function (I/O)
  • Page 67 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (9/23) ML62Q1500 group Pn name Primary function Shared function function SU4_RXD1 function SU4_RXD0 functiion P44/ General I/O pin 12 17 19 DACOUT1 function D/A converter 1 output pin (I/O) function function...
  • Page 68 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (10/23) ML62Q1500 group Pn name Primary function Shared function function function functiion P50/ General I/O pin 24 25 29 33 38 40 EXI8 function External Interrupt 8 (I/O) function function...
  • Page 69 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (11/23) ML62Q1500 group Pn name Primary function Shared function function SU2_RXD1 function SU2_RXD0 functiion 33 43 55 57 General I/O pin function TMH7OUT (I/O) function function function function SU2_TXD1 function...
  • Page 70 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (12/23) ML62Q1500 group Pn name Primary function Shared function function function functiion I2CM1_SCL 41 45 55 71 88 90 General I/O pin function (I/O) function function function function function functiion...
  • Page 71 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (13/23) ML62Q1500 group Pn name Primary function Shared function *1*2*3 function SU3_RXD0/SU3_SIN function functiion P64 / General I/O pin 45 49 59 75 92 94 EXI9 function FTM5P External Interrupt 9 (I/O)
  • Page 72 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (14/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 20 24 29 31 General I/O pin function TMH6OUT (I/O) function function function function function functiion 15 16 19 23 28 30 General I/O pin...
  • Page 73 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (15/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 12 13 16 20 25 27 General I/O pin function (I/O) function function function function function functiion 11 12 15 19 24 26...
  • Page 74 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (16/23) ML62Q1500 group Pn name Primary function Shared function function SU4_RXD0/SU4_SIN function functiion General I/O pin function (I/O) function function function function SU4_TXD0/SU4_SOUT function SU4_TXD1 functiion 10 10 12 General I/O pin function (I/O)
  • Page 75 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (17/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 13 15 General I/O pin function (I/O) function function function function function functiion 14 16 General I/O pin function (I/O)
  • Page 76 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (18/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 42 44 General I/O pin function (I/O) function function function function function functiion 43 45 General I/O pin function (I/O)
  • Page 77 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (19/23) ML62Q1500 group Pn name Primary function Shared function function SU4_TXD0/SU4_SOUT function SU4_TXD1 functiion 38 46 48 General I/O pin function FTM6N (I/O) function function function function SU4_SCLK function functiion...
  • Page 78 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (20/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 50 52 General I/O pin function (I/O) function function function function function functiion 53 55 General I/O pin function (I/O)
  • Page 79 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (21/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 60 72 74 General I/O pin function FTM7N (I/O) function function function AIN15 function function functiion 73 75 General I/O pin...
  • Page 80 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (22/23) ML62Q1500 group Pn name Primary function Shared function function function functiion 76 78 General I/O pin function (I/O) function function function function function functiion 77 79 General I/O pin function (I/O)
  • Page 81 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-8 ML62Q1500 Group Pin List (23/23) ML62Q1500 group Pn name Primary function Shared function function SU5_SCLK function functiion 63 80 General I/O pin function (I/O) function function function function SU5_RXD1 function SU5_RXD0 functiion 64 81 General I/O pin...
  • Page 82 ML62Q1000 Group User's Manual Chapter 1 Overview Talbe 1-9 shows the pin lists of ML62Q1700 group. "(I)" indicates the input pin and "(I/O)" indicates the input/output pin. Table 1-9 ML62Q1700 Group Pin List (1/22) ML62Q1700 group Pin name Primary function Shared function Positive power pin 42 52 54...
  • Page 83 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (2/22) ML62Q1700 group Pin name Primary function Shared function function SU0_SCLK function P04 / General I/O pin functiion I2CU0_SCL EXI2 / External interrupt 2 16 17 21 25 30 32 EXTRG2 / Functional timer external function...
  • Page 84 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (3/22) ML62Q1700 group Pn name Primary function Shared function function SU0_TXD1 function P10 / functiion General I/O pin COM4 / 20 21 25 29 34 36 LCD Common output pin function SEG1 LCD Segment output pin...
  • Page 85 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (4/22) ML62Q1700 group Pn name Primary function Shared function function function functiion P14 / General I/O pin 25 27 35 45 57 59 SEG22 function LCD Segment output pin (I/O) function function...
  • Page 86 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (5/22) ML62Q1700 group Pin name Primary function Shared function function SU0_TXD1 function functiion P20 / General I/O pin 29 31 39 49 61 63 SEG26 function FTM1N LCD Segment output pin (I/O) function...
  • Page 87 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (6/22) ML62Q1700 group Pin name Primary function Shared function function SU1_RXD0/SU1_SIN function functiion P24 / General I/O pin 33 35 43 53 65 67 SEG30 function LCD Segment output pin (I/O) function function...
  • Page 88 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (7/22) ML62Q1700 group Pin name Primary function Shared function function function functiion P30 / General I/O pin 37 41 51 67 84 86 SEG49 function LCD Segment output pin (I/O) function function...
  • Page 89 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (8/22) ML62Q1700 group Pin name Primary function Shared function function SU5_TXD1 function functiion P40 / General I/O pin 49 65 SEG47 function LCD Segment output pin (I/O) function function function...
  • Page 90 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (9/22) ML62Q1700 group Pin name Primary function Shared function function SU4_RXD1 function SU4_RXD0 functiion P44/ General I/O pin 12 17 19 DACOUT1 function FTM3N D/A converter 1 output pin (I/O) function function...
  • Page 91 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (10/22) ML62Q1700 group Pin name Primary function Shared function function function P50/ functiion General I/O pin EXI8/ 24 25 29 33 38 40 External Interrupt 8 function SEG5 LCD Segment output pin function...
  • Page 92 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (11/22) ML62Q1700 group Pn name Primary function Shared function function SU2_RXD1 function SU2_RXD0 functiion P54 / General I/O pin 33 43 55 57 SEG20 function TMH7OUT LCD Segment output pin (I/O) function function...
  • Page 93 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (12/22) ML62Q1700 group Pn name Primary function Shared function function function functiion I2CM1_SCL P60 / General I/O pin 41 45 55 71 88 90 SEG53 function LCD Segment output pin (I/O) function function...
  • Page 94 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (13/22) ML62Q1700 group Pn name Primary function Shared function *1*2*3 function SU3_RXD0/SU3_SIN function P64 / functiion General I/O pin EXI9 / 45 49 59 75 92 94 External Interrupt 9 function FTM5P...
  • Page 95 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (14/22) ML62Q1700 group Pn name Primary function Shared function function function functiion 20 24 General I/O pin function TMH6OUT (I/O) function function function 15 16 19 23 LCD bias power source 3 14 15 18 22 LCD bias power source 2...
  • Page 96 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (15/22) ML62Q1700 group Pn name Primary function Shared function function SU4_RXD0/SU4_SIN function functiion General I/O pin function (I/O) function function function function SU4_TXD0/SU4_SOUT function SU4_TXD1 functiion 10 10 12 General I/O pin function (I/O)
  • Page 97 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (16/22) ML62Q1700 group Pn name Primary function Shared function function SU5_TXD0 function SU5_TXD01 functiion 13 15 General I/O pin function (I/O) function function function function function functiion 14 16 General I/O pin function...
  • Page 98 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (17/22) ML62Q1700 group Pn name Primary function Shared function function function functiion P90 / General I/O pin 42 44 SEG9 function LCD Segment output pin (I/O) function function function function...
  • Page 99 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (18/22) ML62Q1700 group Pn name Primary function Shared function function SU4_TXD0/SU4_SOUT function SU4_TXD1 functiion P94 / General I/O pin 38 46 48 SEG13 function FTM6N LCD Segment output pin (I/O) function function...
  • Page 100 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (19/22) ML62Q1700 group Pn name Primary function Shared function function function functiion PA0 / General I/O pin 50 52 SEG17 function LCD Segment output pin (I/O) function function function function...
  • Page 101 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (20/22) ML62Q1700 group Pn name Primary function Shared function function function functiion PA4 / General I/O pin 60 72 74 SEG37 function FTM7N LCD Segment output pin (I/O) function function...
  • Page 102 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (21/22) ML62Q1700 group Pn name Primary function Shared function function function functiion PB0 / General I/O pin 76 78 SEG41 function LCD Segment output pin (I/O) function function function function...
  • Page 103 ML62Q1000 Group User's Manual Chapter 1 Overview Table 1-9 ML62Q1700 Group Pin List (22/22) ML62Q1700 group Pn name Primary function Shared function function SU5_SCLK function functiion PB4 / General I/O pin 63 80 SEG45 function LCD Segment output pin (I/O) function function function...

  • Page 104: Pin Description

    ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.3 PIN DESCRIPTION Table 1-10 shows the pin list categorized by the function. " " : Power pin, "I": Input pin, "O" Output pin and "I/O" : Input/Output pin Table 1-10 Pin Description Function Signal name Pin name...
  • Page 105 ML62Q1000 Group User's Manual Chapter 1 Overview Function Signal name Pin name Description Logic Positive SU0_TXD0 Serial communication unit0/UART0 data output pin. Positive SU0_RXD0 Serial communication unit0/UART0 data input pin. Positive SU0_TXD1 Serial communication unit0/UART1 data output pin. Positive SU0_RXD1 Serial communication unit0/UART1 data input pin.
  • Page 106 ML62Q1000 Group User's Manual Chapter 1 Overview Function Signal name Pin name Description Logic UART SU5_RXD1 Serial communication unit5/UART1 data input pin. Positive Serial communication unit0/Synchronous serial data input SU0_SIN Positive pin. Serial communication unit0/Synchronous serial clock I/O SU0_SCLK Positive pin.
  • Page 107 ML62Q1000 Group User's Manual Chapter 1 Overview Function Signal name Pin name Description Logic FTM0P 16bit Functional Timer0 output. Positive FTM0N 16bit Functional Timer0 output. Negative FTM1P 16bit Functional Timer1 output. Positive FTM1N 16bit Functional Timer1 output. Negative FTM2P 16bit Functional Timer2 output. Positive FTM2N 16bit Functional Timer2 output.
  • Page 108 ML62Q1000 Group User's Manual Chapter 1 Overview Function Signal name Pin name Description Logic EXI0 External Interrupt 0 Input pin EXI1 External Interrupt 1 Input pin EXI2 External Interrupt 2 Input pin External Interrupt 3 Input pin EXI3 EXI4 External Interrupt 4 Input pin EXI5 External Interrupt 5 Input pin External Interrupt...
  • Page 109 ML62Q1000 Group User's Manual Chapter 1 Overview Signal name Pin name Description Logic Function COM0 Common output pin COM1 Common output pin COM2 Common output pin COM3/SEG0 Common/Segment output shared pin COM4/SEG1 Common/Segment output shared pin COM5/SEG2 Common/Segment output shared pin COM6/SEG3 Common/Segment output shared pin COM7/SEG4...
  • Page 110 ML62Q1000 Group User's Manual Chapter 1 Overview Signal name Pin name Description Logic Function Segment output pin SEG44 Segment output pin SEG45 Segment output pin SEG46 Segment output pin SEG47 Segment output pin SEG48 Segment output pin SEG49 Segment output pin SEG50 Segment output pin SEG51...

  • Page 111: Termination Of Unused Pins

    ML62Q1000 Group User's Manual Chapter 1 Overview 1.3.4 TERMINATION OF UNUSED PINS Table 1-11 shows how to handle the unused pins. Table 1-11 Termination of unused pins Recommended pin termination RESET_N Connect to V through a resistor P00/TEST0 Open the pin with the internal initial condition of pulled-up input mode. XT0/PI00, XT1/PI01 P01 to P07 P10 to P17...

  • Page 112: Cpu And Memory Space

    Chapter 2 CPU and Memory Space...

  • Page 113: General Description

    2. CPU and Memory Space 2.1 General Description ML62Q1000 series has LAPIS Semiconductor's original 16-bit CPU nX-U16/100 (A35 core), the multiplier/divider in the coprocessor, flash memory in the program memory space, and RAM and data flash in the data memory space.
  • Page 114 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space Table 2-3 Program Memory Space and Data Memory Space of ML62Q1700 Group Product name Program memory Data flash size Memory model Data memory space space ROM size RAM size ML62Q1700...

  • Page 115: Cpu Nx-U16/100

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.2 CPU nX-U16/100 nX-U16/100 has following features. See "nX-U16/100 Core Instruction Manual"for details of nX-U16/100. Ÿ Various instruction sets – Instructions for data transfers, arithmetic, comparison, logic operations, bit manipulation, bitwise logic operations, branches, conditional branches, call/return stack manipulation, and arithmetic shifts Ÿ...

  • Page 116: Wait Mode And No-Wait Mode

    2.2.1 Wait Mode and No-wait Mode ML62Q1000 series has two CPU operation modes: wait mode and no-wait mode. The mode can be chosen by Code Option. The maximum CPU operating frequency differs between the wait mode and no-wait mode depending on PLL reference frequency chosen by the Code Option. Table 2-4 shows maximum operating frequency of high-speed clock, peripheral circuit and CPU.

  • Page 117: Coprocessor

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.3 Coprocessor ML62Q1000 series has the built-in multiplier/divider in the coprocessor. The multiplier/divider is operated using coprocessor data transfer instructions of the CPU. For coprocessor data transfer instructions, see "nX-U16/100 Core Instruction Manual".

  • Page 118: List Of Coprocessor General-Purpose Registers

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.3.2 List of Coprocessor General-purpose Registers The coprocessor general-purpose registers are byte type and readable or writable as word type registers (CERn), double word type registers (CXRn), or quad word type registers (CQRn) combining the consecutive registers.
  • Page 119 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.3.2.1 A, B, C, D Registers (CR0 to CR7) These registers store the input values of operations and operation results. These are byte type registers and can be accessed as a word type register (CERn), double word type register (CXRn), or quad word type register (CQRn) combining the consecutive registers.
  • Page 120 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space Quad word symbol CQR0 Double word symbol CXR4 CXR0 Word symbol CER6 CER4 CER2 CER0 Byte symbol Multiplicand Input Multiplier [15:0] Multiplication [15:0] 16 bit x 16 bit Result Product [31:0]...
  • Page 121 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.3.2.2 Operation Mode Register (CR8), Operation Status Register (CR9) The operation mode register (CR8) is a coprocessor general-purpose register to set the operation mode and enables/disables the operation. The operation status register (CR9) is a register to store the status of each operation result.
  • Page 122 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space Bit No. Bit symbol name Description 2 to 0 clmod2 to clmod0 Bits to choose the operation mode. 000: Multiplication 16 bit x 16 bit (initial value) 001: Division 32 bit/16 bit...

  • Page 123: How To Use Multiplier/Divider

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.3.2.3 Coprocessor ID Register (CR15) This is a read-only register to indicate coprocessor ID. The value in CR15 register is fixed to "0x81". It is a byte type register and it can be accessed as a word type register (CERn), double word type register (CXRn), or quad word type register (CQRn) combining the consecutive registers.

  • Page 124: Memory Space

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.4 Memory Space The memory space refers to the address range of the memory that can be specified from the CPU. Figure 2-1 shows the general scheme of the memory space. The memory space of the nX-U16/100 is composed of the program memory space and data memory space.

  • Page 125: Program Memory Space

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.5 Program Memory Space The program memory space is an area to store the program code, vector table, and Code Options. The program memory space is specified by 20 bits (CSR:PC) consisting of higher 4 bits as code segment register (CSR) and lower 16 bits as program counter (PC).
  • Page 126 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space n ML62Q1500 group CSR:PC Segment 0 CSR:PC Segment 0 CSR:PC Segment 0 0x0:0000 Vector table area 0x0:0000 Vector table area 0x0:0000 Vector table area program code area program code area...
  • Page 127 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 CSR:PC Segment 1 0x0:0000 Vector table area 0x1:0000 Program code area program code area 0x0:00FF 0x0:0100 Program code area 0x1:7FBF Code Option area 0x1:7FC0 0x1:7FFF (64 byte)
  • Page 128 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 CSR:PC Segment 1 CSR:PC Segment 2 0x0:0000 Vector table area 0x1:0000 Program code area 0x2:0000 Program code area program code area 0x0:00FF 0x0:0100 Program code area 0x2:7FBF...
  • Page 129 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 CSR:PC Segments 1 to 2 CSR:PC Segment 3 0x0:0000 Vector table area 0xn:0000 0x3:0000 (n=1,2) Program code area Program code area program code area 0x0:00FF 0x0:0100 Program code area...
  • Page 130 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space n ML62Q1700 group CSR:PC Segment 0 CSR:PC Segment 0 CSR:PC Segment 0 0x0:0000 Vector table area 0x0:0000 Vector table area 0x0:0000 Vector table area program code area program code area...
  • Page 131 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 CSR:PC Segment 1 0x0:0000 Vector table area 0x1:0000 Program code area program code area 0x0:00FF 0x0:0100 Program code area 0x1:7FBF Code Option area 0x1:7FC0 0x1:7FFF (64 byte)
  • Page 132 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 CSR:PC Segment 1 CSR:PC Segment 2 0x0:0000 Vector table area 0x1:0000 Program code area 0x2:0000 Program code area program code area 0x0:00FF 0x0:0100 Program code area 0x2:7FBF...
  • Page 133 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 CSR:PC Segments 1 to 2 CSR:PC Segment 3 0x0:0000 Vector table area 0xn:0000 0x3:0000 (n=1,2) Program code area Program code area program code area 0x0:00FF 0x0:0100 Program code area...

  • Page 134: Data Memory Space

    (DSR) and lower 16 bits as data address (address register: AR) specified by each instruction. The 1K byte of test area includes device-specific data, Figures 2-15 to 2-40 show the configuration of the data memory space of ML62Q1000 series products. Other segments not shown in the figures are unused areas.
  • Page 135 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 DSR:AR Segment 8 DSR:AR Segment 31 0x00:0000 0x08:0000 0x1F:0000 Data flash area 0x1F:07FF (2 Kbyte) 0x1F:0800 ROM window area Mirror area (32 Kbyte) (32 Kbyte) 0x00:7FFF 0x08:7FFF...
  • Page 136 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 DSR:AR Segment 8 DSR:AR Segment 31 0x00:0000 0x08:0000 0x1F:0000 Data flash area 0x1F:07FF (2 Kbyte) 0x1F:0800 ROM window area Mirror area (48 Kbyte) (32 Kbyte) 0x00:BFFF 0x08:BFFF...
  • Page 137 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space n ML62Q1500 group DSR:AR Segment 0 DSR:AR Segment 8 DSR:AR Segment 31 0x00:0000 0x08:0000 0x1F:0000 Data flash area 0x1F:0FFF (4 Kbyte) 0x1F:1000 ROM window area Mirror area (32 Kbyte) (32 Kbyte)
  • Page 138 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 0x00:0000 ROM window area (52 Kbyte) 0x00:D000 RAM area 0x00:EFFF 8 Kbyte 0x00:F000 SFR area 0x00:FFFF 8 bit DSR:AR Segment 8 DSR:AR Segment 9 DSR:AR Segment 31...
  • Page 139 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 DSR:AR Segment 1 0x00:0000 ROM window 0x01:0000 Mirror area area (32 Kbyte) (44 Kbyte) 0x01:7FFF 0x01:8000 0x00:B000 RAM area 0x01:8FFF 0x00:EFFF 16 Kbyte 0x01:9000 Unused area 0x00:F000...
  • Page 140 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 DSR:AR Segment 1 0x00:0000 ROM window 0x01:0000 Mirror area area (64 Kbyte) (44 Kbyte) 0x00:B000 RAM area 0x00:EFFF 16 Kbyte 0x00:F000 SFR area 0x00:FFFF 0x01:FFFF 8 bit...
  • Page 141 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 DSR:AR Segments 1 to 2 0x00:0000 ROM window 0x01 to 2:0000 Mirror area area (64 Kbyte) (44 Kbyte) 0x00:B000 RAM area 0x00:EFFF 16 Kbyte 0x00:F000 SFR area...
  • Page 142 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space n ML62Q1700 group DSR:AR Segment 0 DSR:AR Segment 8 DSR:AR Segment 31 0x00:0000 0x08:0000 0x1F:0000 Data flash area 0x1F:0FFF (4 Kbyte) 0x1F:1000 ROM window area Mirror area (32 Kbyte) (32 Kbyte)
  • Page 143 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 0x00:0000 ROM window area (52 Kbyte) 0x00:D000 RAM area 0x00:EFFF 8 Kbyte 0x00:F000 SFR area 0x00:FFFF 8 bit DSR:AR Segment 8 DSR:AR Segment 9 DSR:AR Segment 31...
  • Page 144 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 DSR:AR Segment 1 0x00:0000 ROM window 0x01:0000 Mirror area area (32 Kbyte) (44 Kbyte) 0x01:7FFF 0x01:8000 0x00:B000 RAM area 0x01:8FFF 0x00:EFFF 16 Kbyte 0x01:9000 Unused area 0x00:F000...
  • Page 145 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 DSR:AR Segment 1 0x00:0000 ROM window 0x01:0000 Mirror area area (64 Kbyte) (44 Kbyte) 0x00:B000 RAM area 0x00:EFFF 16 Kbyte 0x00:F000 SFR area 0x00:FFFF 0x01:FFFF 8 bit...
  • Page 146 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space DSR:AR Segment 0 DSR:AR Segments 1 to 2 0x00:0000 ROM window 0x01 to 2:0000 Mirror area area (64 Kbyte) (44 Kbyte) 0x00:B000 RAM area 0x00:EFFF 16 Kbyte 0x00:F000 SFR area...
  • Page 147 ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space [Note] Ÿ The contents of the RAM area are undefined at power-on and system reset. Initialize this area by the software. Ÿ The 1K byte (512 word) of Test area includes device-specific data, are unavailable to use as the program code area.

  • Page 148: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.7 Description of Registers 2.7.1 List of Registers Symbol name Initial Address Name Size value Byte Word 0xF000 Data segment register 0x00 0xF0A0 Flash remap address register REMAPADD 0x00 FEUL62Q1000...

  • Page 149: Data Segment Register (Dsr)

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.7.2 Data Segment Register (DSR) DSR is a special function register (SFR) used to specify a data segment. See "nX-U16/100 Core Instruction Manual" for details of DSR. Address: 0xF000(DSR) Access:...

  • Page 150: Flash Remap Address Register (Remapadd)

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.7.3 Flash Remap Address Register (REMAPADD) REMAPADD is a special function register (SFR) used to specify the 4 Kbyte area to be remapped. Address: 0xF0A0 (REMAPADD) Access: Access size: 8 bit...

  • Page 151: Remapping Function

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.8 Remapping Function The remapping function replaces the addresses 0x0000 to 0x0FFF (initial boot area) in the program memory space with the specified arbitrary 4 Kbyte area. Figure 2-41 shows the general scheme of the remapping function.

  • Page 152: Description Of Remapping Function

    Address Register (FLASHA). Refer to "ML62Q1000 Series Reference Software" for specific details on how to use the remapping function. Refer to "ML62Q1000 Series IAP Sample Program" for how to re-write the user application program on the flash memory using the remapping function.

  • Page 153: Code Option Remap

    ML62Q1000 Series User's Manual Chapter 2 CPU and Memory Space 2.8.3 Code Option Remap By setting CREMAPMD, CRES1-0, CREA15-CREA12 of the Code Options 2(CODEOP2). The LSI always start at the sytem reset on the remap condtion. Ÿ If setting both REMAPMD and CREMAPMD to "0", the LSI starts running at the address set in CRES1-0 and CREA15-CREA12.

  • Page 154: Reset Function

    Chapter 3 Reset Function...

  • Page 155: General Description

    Reset Function 3.1 General Description ML62Q1000 series has a function to reset the CPU, peripheral circuits and other hardware due to the causes described below. This chapter describes the system reset mode, reset input pin reset and power-on reset (POR). See reference chapters for other causes of resets.

  • Page 156: Features

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.1.1 Features Each reset can uniquely be managed depending on its cause as this function contains following features to identify the cause in an early stage. · Reset status register (RSTAT) to indicate the cause of the reset ·...

  • Page 157: Configuration

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.1.2 Configuration Figure 3-1 shows the configuration of the reset generation circuit. RESET_N Reset signal to the CPU, peripheral circuits, and other circuits Power-on reset WDT overflow reset WDT invalid clear reset...

  • Page 158: List Of Pins

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.1.3 List of Pins Pin name Function RESET_N Reset input pin FEUL62Q1000...

  • Page 159: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.2 Description of Registers 3.2.1 List of Registers Symbol name Address Name Size Initial value Byte Word 0xF058 RSTATL 8/16 Undefined Reset status register RSTAT 0xF059 RSTATH Undefined 0xF05A Safety function reset status register...

  • Page 160: Reset Status Register (Rstat)

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.2.2 Reset status register (RSTAT) RSTAT is a special function register (SFR) to indicate the cause of occurrence of a reset. When a reset occurs, only the bit that indicates the cause of the reset occurred is set to "1". Other bits (except the INITE bit) retain values before occurrence of the reset.
  • Page 161 ML62Q1000 Series User's Manual Chapter 3 Reset Function Bit symbol Description name A bit to indicate that a power-on reset has occurred. This bit is reset to "0" when "1" is written. 0: No power-on reset occurred 1: Power-on reset occurred...

  • Page 162: Safety Function Reset Status Register (Srstat)

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.2.3 Safety Function Reset Status Register (SRSTAT) SRSTAT is a special function register (SFR) to indicate the cause of occurrence of a safety function reset. When the safety function reset occurs, only the bit that indicates the cause of the reset occurred is set to "1". Other bits retain values before occurrence of the reset.

  • Page 163: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.3 Description of Operation 3.3.1 Operation of Reset Function Table 3-2 shows the availability of resets for each cause. Table 3-2 Availability of Resets for Each Cause Peripheral Voltage level Cause *Hardware...

  • Page 164: System Reset Mode

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.3.2 System Reset Mode The LSI is transferred to the system reset mode when a reset occurs by any cause, except for resets caused by the block control register (BRECON 0 to 3) and the software reset control register (SOFTRCON) as well as a CPU reset by the BRK instruction.

  • Page 165: Power-On Reset

    ML62Q1000 Series User's Manual Chapter 3 Reset Function 3.3.4 Power-on Reset The power-on reset occurs when detecting the start-up of the power (V ), or when the power voltage (V ) decreases 100 mV or more below the power-on reset trigger voltage (V ) and after the power-on reset reaction time (T elapses.

  • Page 166: Power Management

    Chapter 4 Power Management...

  • Page 167: General Description

    ML62Q1000 Series User's Manual Chapter 4 Power Management Power Management 4.1 General Description ML62Q1000 series has four power management modes to save the current consumption. · HALT mode : Stop the CPU and peripherals continue to work. · HALT-H mode : Stop the CPU, peripherals continue to work with low-speed clock only, forcely stop high-speed clock and restart the high-speed clcok after releasing the mode.

  • Page 168: Features

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.1.1 Features · Stop code accceptor qualifies for entering STOP mode and STOP-D mode · Data of RAM and SFR are retained even in the STOP-D mode · Clock supply is control-able peripheral by peripheral to reduce the current consumption, by block clock control registers ·...

  • Page 169: Configuration

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.1.2 Configuration Figure 4-1 shows the transition diagram of the operating state. The bit symbols in the figure are assigned to the standby control register (SBYCON). Reset released Power on Program System reset...

  • Page 170: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2 Description of Registers 4.2.1 List of Registers Symbol Name Initial Address Name Size value Byte Word 0xF018 Stop code acceptor STPACP 0x00 0xF019 Reserved register 0x00 0xF01A Standby control register L...

  • Page 171: Stop Code Acceptor (Stpacp)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.2 Stop Code Acceptor (STPACP) STPACP is a write-only specific function register (SFR) to be used to change the operating state into the STOP mode and STOP-D mode. The STPACP returns "0x00" for reading.

  • Page 172: Standby Control Register (Sbycon)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.3 Standby Control Register (SBYCON) SBYCON is a write-only specific function register (SFR) to choose a standby mode. The SBYCON returns "0x0000" for reading. Address: 0xF01A(SBYCONL/SBYCON), 0xF01B(SBYCONH) Access: Access size: 8/16bit Initial value:...

  • Page 173: Software Reset Acceptor (Softracp)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.4 Software Reset Acceptor (SOFTRACP) SOFTRACP is a write-only specific function register (SFR) to enable collectively reseting the all peripheral circuits belong to the BRECONn register (n=0 to 3). The SOFTRACP returns "0x00" for reading.

  • Page 174: Software Reset Control Register (Softrcon)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.5 Software Reset Control Register (SOFTRCON) SOFTRCON is a specific function register (SFR) to reset collectively the all peripheral circuits belong to the BRECONn register (n=0 to 3) and general ports. Address:...

  • Page 175: Block Clock Control Register 0 (Bckcon0)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.6 Block Clock Control Register 0 (BCKCON0) BCKCON0 is a specific function register (SFR) to control supplying the clock of high-speed and low-speed to the peripheral circuits. The power consumption can be reduced by stopping the clock supply for unused peripheral circuits.

  • Page 176: Block Clock Control Register 1 (Bckcon1)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.7 Block Clock Control Register 1 (BCKCON1) BCKCON1 is a specific function register (SFR) to control supplying the clock of high-speed and low-speed to the peripheral circuits. The power consumption can be reduced by stopping the clock supply for unused peripheral circuits.
  • Page 177 ML62Q1000 Series User's Manual Chapter 4 Power Management Bit symbol Bit No. Description name DCKFTM2 This bit controls the clock supply for the peripheral circuit of Functional Timer 3. Enable supplying the clock to the peripheral circuit (initial value) Stop supplying the clock to the peripheral circuit DCKFTM1 This bit controls the clock supply for the peripheral circuit of Functional Timer 2.

  • Page 178: Block Clock Control Register 2 (Bckcon2)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.8 Block Clock Control Register 2 (BCKCON2) BCKCON2 is a specific function register (SFR) to control supplying the clock of high-speed and low-speed to the peripheral circuits. The power consumption can be reduced by stopping the clock supply for unused peripheral circuits.
  • Page 179 ML62Q1000 Series User's Manual Chapter 4 Power Management Bit symbol Bit No. Description name DCKSU0 This bit controls the clock supply for the peripheral circuit of Serial Communication Unit 0. Enable supplying the clock to the peripheral circuit (initial value)

  • Page 180: Block Clock Control Register 3 (Bckcon3)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.9 Block Clock Control Register 3 (BCKCON3) BCKCON3 is a specific function register (SFR) to control supplying the clock of high-speed and low-speed to the peripheral circuits. The power consumption can be reduced by stopping the clock supply for unused peripheral circuits.

  • Page 181: Block Reset Control Register 0 (Brecon0)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.10 Block Reset Control Register 0 (BRECON0) BRECON0 is a specific function register (SFR) to control reseting the peripheral circuits. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.

  • Page 182: Block Reset Control Register 1 (Brecon1)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.11 Block Reset Control Register 1 (BRECON1) BRECON1 is a specific function register (SFR) to control reseting the peripheral circuits. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 183 ML62Q1000 Series User's Manual Chapter 4 Power Management Bit symbol Bit No. Description name RSEFTM1 This bit controls to reset the peripheral circuit of Functional Timer 1. Cancel to reset the peripheral circuit (initial value) Remain to reset the peripheral circuit RSEFTM0 This bit controls to reset the peripheral circuit of Functional Timer 0.

  • Page 184: Block Reset Control Register 2 (Brecon2)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.12 Block Reset Control Register 2 (BRECON2) BRECON2 is a specific function register (SFR) to control reseting the peripheral circuits. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 185 ML62Q1000 Series User's Manual Chapter 4 Power Management [Note] Ÿ The DCKACC bit can be set to "1" when the multiplication/division library "muldivu8.lib" is not specified in the target option of the Integrated Development Environment IDEU8. Ÿ To restart the operation of the peripheral circuits, reset them at first by the block reset control regiser (BRECON2) and then cancel the reset after enabling the clock supply by the block clock control register (BCKCON2).

  • Page 186: Block Reset Control Register 3 (Brecon3)

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.2.13 Block Reset Control Register 3 (BRECON3) BRECON3 is a specific function register (SFR) to control reseting the peripheral circuits. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.

  • Page 187: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.3 Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. When a reset is released after the reset is generated, the operating state is transferred from the system reset mode to the program run mode.

  • Page 188: Halt-H Mode

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.3.3 HALT-H Mode In the HALT-H mode, HSCLK is forcibly stopped, the CPU stops, and only peripheral circuits remain in operation. Note that the peripheral circuits in operation with the HSCLK stop operating in the HALT-H mode. See "4.1.7 Operation of Each Function in Standby Mode"...

  • Page 189: Stop Mode

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.3.4 STOP Mode The STOP mode is the state where LSCLK and HSCLK are forcibly stopped, and both the CPU and the peripheral circuit which requires the clock stop operating. See "4.1.7 Operation of Each Function in Standby Mode" for operation of each function in the STOP mode.

  • Page 190: Stop-D Mode

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.3.5 STOP-D Mode The STOP-D mode has, in addition to the functionality of the STOP mode described in the previous section, an additional control function to decrease the voltage of internal logic power (V ).

  • Page 191: Note On Return Operation From The Standby Mode

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.3.6 Note on Return Operation from Standby Mode The operation of returning the standby mode is caused by the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the register (IE0 to IE7), non-maskable interrupt, or maskable interrupt.

  • Page 192: Operation Of Each Function In Standby Mode

    ML62Q1000 Series User's Manual Chapter 4 Power Management 4.3.7 Operation of Each Function in Standby Mode Table 4-4 shows the state of each function block in the standby mode. Table 4-4 State of Each Function in Standby Mode Function block...
  • Page 193 ML62Q1000 Series User's Manual Chapter 4 Power Management Table 4-5 shows the wake-up time (restoring time) from the standby modes. See Chapter 6 "Clock Generation Circuit" for details of the FHWUPT register. Table 4-5 Wake-up Time from Standby Mode Low-speed clock...

  • Page 194: Block Control Function

    Chapter 4 Power Management 4.3.8 Block Control Function ML62Q1000 series has the block clock control function that stops clock supply for each peripheral circuit to reduce current consumption and the block reset control function to reset each peripheral circuit. When setting each bit of the BCKCONn registers (n=0 to 3) to "1", it stops supplying the clock to the corresponding peripheral circuits reducing the current consumption.
  • Page 195 ML62Q1000 Series User's Manual Chapter 4 Power Management In the state where clock supply to each peripheral circuit is suspended or in the reset state, writing to SFRs of corresponding peripheral circuits is disabled. The initial values are read for reading the SFRs of peripheral circuits.

  • Page 196: Interrupts

    Chapter 5 Interrupts...

  • Page 197: General Description

    Chapter 5 Interrupts Interrupt 5.1 General Description ML62Q1000 series has the non-maskable interrupt, maskable interrupts and the software interrupt (SWI). For details of each interrupt, see the corresponding Chapters. See Chapter 29 "Safety Function" for the MCU status interrupt. See "Table 1-2 Main Function List" in the Chapter 1 to confirm the presence/absence of function in each product.

  • Page 198: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2 Description of Registers 5.2.1 List of Registers Symbol name Initial Address Name Size value Byte Word 0xF020 8/16 0x00 Interrupt enable register 01 IE01 0xF021 0x00 0xF022 8/16 0x00 Interrupt enable register 23...
  • Page 199 ML62Q1000 Series User's Manual Chapter 5 Interrupts The interrupt souces are devendent of the product specification. Table 5-1 shows presence/absence of interrupt source in each product. Table 5-1 List of Interrupt Source (1/2) Register assignment Interrupt 48pin 52pin 64 pin...
  • Page 200 ML62Q1000 Series User's Manual Chapter 5 Interrupts Table 5-1 List of Interrupt Source (2/2) Register assignment Interrupt 48pin 52pin 64 pin 80 pin 100 pin Interrupt source source (interrupt (interrupt (interrupt Product Product Product Product Product symbol request) request) request) Serial Communication Unit 20 ●...

  • Page 201: Interrupt Enable Register 01 (Ie01)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.2 Interrupt Enable Register 01 (IE01) IE01 is a specific function register (SFR) to enable or disable the interrupt for each interrupt request. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.

  • Page 202: Interrupt Enable Register 23 (Ie23)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.3 Interrupt Enable Register 23 (IE23) IE23 is a specific function register (SFR) to enable or disable the interrupt for each interrupt request. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 203 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit symbol Bit No. Description name ESIU01 This bit controls to enable or disable the Serial Communication unit 01 interrupt (SIU01INT). Disable the interrupt (initial value) Enable the interrupt ESIU00 This bit controls to enable or disable the Serial Communication unit 00 interrupt (SIU00INT).

  • Page 204: Interrupt Enable Register 45 (Ie45)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.4 Interrupt Enable Register 45 (IE45) IE45 is a specific function register (SFR) to enable or disable the interrupt for each interrupt request. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 205 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit symbol Bit No. Description name EFTM3 This bit controls to enable or disable the Functional Timer 3 interrupt (FTM3INT). Disable the interrupt (initial value) Enable the interrupt EFTM2 This bit controls to enable or disable the Functional Timer 2 interrupt (FTM2INT).

  • Page 206: Interrupt Enable Register 67 (Ie67)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.5 Interrupt Enable Register 67 (IE67) IE67 is a specific function register (SFR) to enable or disable the interrupt for each interrupt request. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 207 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit symbol Bit No. Description name EFTM6 This bit controls to enable or disable the Functional Timer 6 interrupt (FTM6INT). Disable the interrupt (initial value) Enable the interrupt ESIU41 This bit controls to enable or disable the Serial Communication unit 41 interrupt (SIU41INT).

  • Page 208: Interrupt Request Register 01 (Irq01)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.6 Interrupt Request Register 01 (IRQ01) IRQ01 is a specific function register (SFR) to request interrupts. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 209 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit symbol Bit No. Description name QPI0 This bit controls to request the External interrupt 1 (EXI1INT). Not request the interrupt (initial value) Request the interrupt Reserved bit QVLS0 This bit controls to request the VLS0 interrupt (VLS0INT).

  • Page 210: Interrupt Request Register 23 (Irq23)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.7 Interrupt Request Register 23 (IRQ23) IRQ23 is a specific function register (SFR) to request interrupts. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 211 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit symbol Bit No. Description name This bit controls to request the Successive approximation type A/D interrupt (SADINT). QSAD Not request the interrupt (initial value) Request the interrupt Reserved bit This bit controls to request the Serial Communication unit 01 interrupt (SIU01INT).

  • Page 212: Interrupt Request Register 45 (Irq45)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.8 Interrupt Request Register 45 (IRQ45) IRQ45 is a specific function register (SFR) to request interrupts. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 213 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit symbol Bit No. Description name This bit controls to request the 16bit Timer 3 interrupt (TM3INT). QTM3 Not request the interrupt (initial value) Request the interrupt This bit controls to request the 16bit Timer 2 interrupt (TM2INT).

  • Page 214: Interrupt Request Register 67 (Irq67)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.9 Interrupt Request Register 67 (IRQ67) IRQ67 is a specific function register (SFR) to request interrupts. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 215 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit symbol Bit No. Description name This bit controls to request the 16bit Timer 6 interrupt (TM6INT). QTM6 Not request the interrupt (initial value) Request the interrupt This bit controls to request the Functional Timer 7 interrupt (FTM7INT).

  • Page 216: Interrupt Level Control Enable Register (Ilen)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.10 Interrupt Level Control Enable Register (ILEN) ILEN is a specific function register (SFR) to enable or disable the interrupt level control. Address: 0xF030(ILEN) Access: Access size: 8bit Initial value: 0x00 Word Byte...

  • Page 217: Current Interrupt Level Management Register (Cil)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.11 Current Interrupt Level Management Register (CIL) CIL is a specific function register (SFR) to manage the priority level of the interrupt currently being processed by the CPU. After maskable or non-maskable interrupts to which the priority levels are specified by the interrupt level control registers (ILC0 to 7) is accepted by the CPU, corresponding bits of CIL are automatically set to "1", indicate the...

  • Page 218: Interrupt Level Control Register 0 (Ilc0)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.12 Interrupt Level Control Register 0 (ILC0) ILC0 is a specific function register (SFR) to set the interrupt level for each maskable interrupt source. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.

  • Page 219: Interrupt Level Control Register 1 (Ilc1)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.13 Interrupt Level Control Register 1 (ILC1) ILC1 is a specific function register (SFR) to set the interrupt level for each maskable interrupt source. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 220 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit No. Bit symbol name Description ILPI1H, ILPI1L This bit chooses the priority level of the External interrupt 1 (EXI1INT). 00: Level 1 (Priority is lowest) (initial) 01: Level 2 10: Level 3...

  • Page 221: Interrupt Level Control Register 2 (Ilc2)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.14 Interrupt Level Control Register 2 (ILC2) ILC2 is a specific function register (SFR) to set the interrupt level for each maskable interrupt source. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 222 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit No. Bit symbol name Description ILCBUH, ILCBUL This bit chooses the priority level of the Clock Backup interrupt (CBUINT). 00: Level 1 (Priority is lowest) (initial) 01: Level 2 10: Level 3 11: Level 4 (Priority is highest) "...

  • Page 223: Interrupt Level Control Register 3 (Ilc3)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.15 Interrupt Level Control Register 3 (ILC3) ILC3 is a specific function register (SFR) to set the interrupt level for each maskable interrupt source. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 224 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit No. Bit symbol name Description Reserved bit ILEXTXH, ILEXTXL This bit chooses the priority level of the External expanded interrupt ( EXTXINT 00: Level 1 (Priority is lowest) (initial) 01: Level 2...

  • Page 225: Interrupt Level Control Register 4 (Ilc4)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.16 Interrupt Level Control Register 4 (ILC4) ILC4 is a specific function register (SFR) to set the interrupt level for each maskable interrupt source. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 226 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit No. Bit symbol name Description ILSIU10H, ILSIU10L This bit chooses the priority level of the Serial Communication unit 10 interrupt (SIU10INT). 00: Level 1 (Priority is lowest) (initial) 01: Level 2 10: Level 3...

  • Page 227: Interrupt Level Control Register 5 (Ilc5)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.17 Interrupt Level Control Register 5 (ILC5) ILC5 is a specific function register (SFR) to set the interrupt level for each maskable interrupt source. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 228 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit No. Bit symbol name Description ILSIU21H, ILSIU21L * This bit chooses the priority level of the Serial Communication unit 21 interrupt (SIU21INT). 00: Level 1 (Priority is lowest) (initial) 01: Level 2...

  • Page 229: Interrupt Level Control Register 6 (Ilc6)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.18 Interrupt Level Control Register 6 (ILC6) ILC6 is a specific function register (SFR) to set the interrupt level for each maskable interrupt source. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 230 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit No. Bit symbol name Description ILSIU31H, ILSIU31L This bit chooses the priority level of the Serial Communication unit 31 interrupt (SIU31INT). 00: Level 1 (Priority is lowest) (initial) 01: Level 2 10: Level 3...

  • Page 231: Interrupt Level Control Register 7 (Ilc7)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.2.19 Interrupt Level Control Register 7 (ILC7) ILC7 is a specific function register (SFR) to set the interrupt level for each maskable interrupt source. The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
  • Page 232 ML62Q1000 Series User's Manual Chapter 5 Interrupts Bit No. Bit symbol name Description ILSIU50H, ILSIU50L This bit chooses the priority level of the Serial Communication unit 50 interrupt (SIU50INT). 00: Level 1 (Priority is lowest) (initial) 01: Level 2 10: Level 3...

  • Page 233: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.3 Description of Operation Enabling/disabling the maskable interrupt can be controlled by the master interrupt enable flag (MIE) of the CPU and each interrupt enable register (IE1 to 7). A watchdog timer interrupt (WDTINT) is unavailable to disable as it is a non-maskable interrupt.
  • Page 234 ML62Q1000 Series User's Manual Chapter 5 Interrupts Table 5-2 List of Interrupt Sources (1/2) Register assignment Interrupt Interrupt External/ Interrupt source vector Mask internal Interrupt source source number (interrupt (interrupt (interrupt address source symbol (priority) request) enable) level) 1 (high)
  • Page 235 ML62Q1000 Series User's Manual Chapter 5 Interrupts Table 5-2 List of Interrupt Sources (2/2) Register assignment Interrupt Interrupt External/ Interrupt source vector Mask internal Interrupt source source ILC (interrupt number (interrupt (interrupt address source symbol level) (priority) request) enable) IRQ4[6]...

  • Page 236: Maskable Interrupt Processing

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.3.1 Maskable Interrupt Processing When an interrupt is generated with MIE set to "1", the following process is executed by hardware and the CPU goes to the interrupt routine. Save the program counter (PC) in ELR1.

  • Page 237: Notes On Interrupt Routine (With Interrupt Level Control Disabled)

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.3.4 Notes on Interrupt Routine (with Interrupt Level Control Disabled) Writing "0" to the ILE bit of the interrupt level control enable register (ILEN) causes the interrupt level control to be disabled. The description below shows notes on each of the following states when the interrupt level control is not in use.
  • Page 238 ML62Q1000 Series User's Manual Chapter 5 Interrupts A-1-2: When multiple interrupts are enabled • When the script is written in the assembly language • Processing immediately after the start of interrupt routine execution Specify "PUSH ELR, EPSW" to save the interrupt return address and the PSW status in the stack.
  • Page 239 ML62Q1000 Series User's Manual Chapter 5 Interrupts A-2: When a subroutine is called in an interrupt routine A-2-1: When multiple interrupts are disabled • When the script is written in the assembly language • Processing immediately after the start of interrupt routine execution Specify the "PUSH LR"...
  • Page 240 ML62Q1000 Series User's Manual Chapter 5 Interrupts A-2-2: When multiple interrupts are enabled • When the script is written in the assembly language • Processing immediately after the start of interrupt routine execution Specify "PUSH LR, ELR, EPSW, LR" to save the interrupt return address, the subroutine return address, and the EPSW1 status in the stack.
  • Page 241 ML62Q1000 Series User's Manual Chapter 5 Interrupts State B: Non-maskable interrupt is being processed B-1: When a subroutine is not called in an interrupt routine • When the script is written in the assembly language • Processing immediately after the start of interrupt routine execution Specify "PUSH ELR, EPSW"...
  • Page 242 ML62Q1000 Series User's Manual Chapter 5 Interrupts B-2: When a subroutine is called in an interrupt routine • When the script is written in the assembly language • Processing immediately after the start of interrupt routine execution Specify "PUSH ELR, EPSW, LR" to save the interrupt return address, the subroutine return address, and EPSW status in the stack.

  • Page 243: Flow Charts When Interrupt Level Control Is Enabled

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.3.5 Flow Charts When Interrupt Level Control Is Enabled Figure 5-1 shows flow charts of the software interrupt processing when multiple interrupts are disabled and enabled respectively with the interrupt level control enabled.

  • Page 244: How To Write Interrupt Processing When Interrupt Level Control Enabled

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.3.6 How To Write Interrupt Processing When Interrupt Level Control Enabled This section describes examples of program scripts of interrupt function when ILE of the interrupt level control enable register (ILEN) is set to enable the interrupt level control. See "CCU8 Programming Guide" for the detailed scripting method of and notes on interrupt processing.
  • Page 245 ML62Q1000 Series User's Manual Chapter 5 Interrupts In the interrupt function, the register (here, only ER0) that may be used in the interrupt routine is saved in the stack. "RTI" instruction is used to return from the interrupt function to disable multiple interrupts.
  • Page 246 ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.3.6.2 Description of Interrupt Function to Enable Multiple Interrupts When describing an interrupt function to enable multiple interrupts, specify "2" in the category field in INTERRUPT pragma and SWI pragma. Even if it is not specified in the category field, multiple interrupt are enabled. Built-in function_EI can be called in an interrupt function to enable multiple interrupts.

  • Page 247: Interrupt Disable State

    ML62Q1000 Series User's Manual Chapter 5 Interrupts 5.3.7 Interrupt Disable State The interrupt disable state refers to an operating state where no interrupt is accepted even if the interrupt conditions are satisfied. The following describes the interrupt disabled state and operation of interrupts in the situation.

  • Page 248: Clock Generation Circuit

    Chapter 6 Clock generation Circuit...

  • Page 249: General Description

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit Clock Generation Circuit 6.1 General Description The clock generation circuit generates following kinds of clock and supplied them to the CPU or the peripheral circuits. Table 6-1 Clocks generated by the clock generation circuit...

  • Page 250: Configuration

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.1.2 Configuration Figure 6-1 shows the configuration of the clock generation circuit. Table 6-3 shows the list of operation clocks for each function. Code option Approx.1kHz RC1K oscillation WDTCLK Low-speed Approx.1.024kHz...

  • Page 251: List Of Pins

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit Table 6-3 Operating clock list in each function Simplified RTC High speed Low-speed System clock WDT clock clock clock Function clock SYSTEMCLK WDTCLK LSCLK RTCCLK* HSCLK ● ● ● ● Watchdog timer ●...

  • Page 252: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2 Description of Registers 6.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF002 FHCKMODL 8/16 0x00 High-speed clock mode register FHCKMOD 0xF003 FHCKMODH 0x44 0xF004 Low-speed clock mode register *...

  • Page 253: High-Speed Clock Mode Register (Fhckmod)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.2 High-Speed Clock Mode Register (FHCKMOD) FHCKMOD is a specific function register (SFR) to choose the oscillation mode of the high-speed clock oscillation circuit (PLL oscillation circuit) and the frequency of high-speed clock.
  • Page 254 ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit [Note] Ÿ When the voltage of VDD is 1.6V≦VDD＜1.8V, set the system clock to 4 MHz or lower. If it exceeds 4MHz, the operation is not guaranteed. Ÿ For output of the high-speed clock (OUTHSCLK), the output clock frequency is limited according to the voltage of VDD.

  • Page 255: Low-Speed Clock Mode Register (Flmod)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.3 Low-speed Clock Mode Register (FLMOD) FLMOD is a specific function register (SFR) to control the low-speed clock (LSCLK). The FLMOD is initialized by only the Power-On-Reset. This register is unavailable on the ML62Q1300 group.

  • Page 256: Clock Control Register (Fcon)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.4 Clock Control Register (FCON) FCON is a specific function register (SFR) to control the clock generation circuit and choose the system clock. Address: 0xF006 Access: Access size: 8 bits Initial value: 0x00...

  • Page 257: High-Speed Clock Wake-Up Time Setting Register (Fhwupt)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.5 High-Speed Clock Wake-up Time Setting Register (FHWUPT) FHWUPT is a specific function register (SFR) to choose the wake-up time of the high-speed clock. FHWUPT is writable only when the high-speed oscillation is stopped.

  • Page 258: Backup Control Register (Fbucon)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.6 Backup Control Register (FBUCON) FBUCON is a specific function register (SFR) to switch the backup clock. This register is unavailable on the ML62Q1300 group. The FBUCON is used only when choosing the low-speed crystal oscillation clock.

  • Page 259: Backup Clock Status Register (Fbustat)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.7 Backup Clock Status Register (FBUSTAT) FBUSTAT is a specific function register (SFR) to indicate status of low-speed oscillation clock. This register is unavailable on the ML62Q1300 group. The FBUSTAT is used only when choosing the low-speed crystal oscillation clock.

  • Page 260: Clock Backup Test Mode Acceptor (Fbtacp)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.8 Clock Backup Test Mode Acceptor (FBTACP) FBTACP is a specific function register (SFR) to enable writing to Clock Backup Test Mode register (FBTCON). This register is unavailable on the ML62Q1300 group.

  • Page 261: Clock Backup Test Mode (Fbtcon)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.9 Clock Backup Test Mode (FBTCON) FBTCON is a specific function register (SFR) to control the clock backup test mode. This register is unavailable on the ML62Q1300 group. The clock backup test mode can make purposely the condition that stops the low-speed crystal oscillation.

  • Page 262: Low-Speed Rc Oscillation Frequency Adjustment Register (Lrcadj)

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.2.10 Low-Speed RC Oscillation Frequency Adjustment Register (LRCADJ) LRCADJ is a specific function register (SFR) to adjust the frequency of the low-speed RC oscillation clock. Use the RC oscillation adjustment sample software provided by LAPIS.

  • Page 263: Description Of Operation

    10 counts of the low-speed RC oscillation clock. The frequency of the low-speed RC oscillation circuit can be adjusted with the low-speed RC oscillation frequency adjustment register (LRCADJ). To adjust the frequency, use the sample software "ML62Q1000 Series RC oscillation adjustment sample software" provided by LAPIS.
  • Page 264 ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit Power supply V Power-on reset Low-speed RC clock Oscillation waveform 10 counts 512 counts (approx. 320 μs) oscillation (approx. 16 ms) Low-speed clock waveform RC oscillation (LSCLK) waveform STOP/STOP-D mode LSCLK supply...
  • Page 265 ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.3.1.2 Configuration of Low-Speed Crystal Oscillation Circuit Figure 6-5 shows the configuration of the low-speed crystal oscillation circuit. This circuit is unavailable on the ML62Q1300 group. The 32.768 kHz crystal oscillator can be chosen in the low-speed clock mode register (FLMOD).
  • Page 266 ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit Figure 6-6 describes backup mode waveforms at the start of the low-speed crystal clock and in the STOP/STOP-D mode. The low-speed crystal oscillation circuit operates when choosing it through the low-speed clock mode register (FLMOD) following the start of low-speed RC oscillation circuit operation after the power supply is turned on.
  • Page 267 ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit Figure 6-7 describes operation waveforms in the backup mode after the start of the low-speed crystal clock. Following the start of the low-speed crystal, the state on the LSI transfers to the backup mode if the crystal oscillation clock stops for approximately 8 ms.
  • Page 268 ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit Figure 6-8 shows the operation waveforms when a reset occurs after the start of the low-speed crystal clock. The low-speed crystal oscillation circuit is not reset by anything but the power-on reset.

  • Page 269: High-Speed Clock

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.3.2 High-speed Clock The high-speed clock is generated by multiplying the low-speed clock (LSCLK) by the high-speed oscillation circuit (PLL oscillation circuit). The oscillation frequency of PLL can be chosen from 24 MHz or 16 MHz through the code option.

  • Page 270: Wdt Clock

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.3.3 WDT Clock For the WDT clock (WDTCLK), the clock with divided frequency of low-speed clock (1.024 kHz) or the WDT dedicated RC1K oscillation clock (approx. 1 kHz) can be chosen by the code option. If the accuracy of the watch dog timer is required, choose the clock with divided frequency of the low-speed clock.

  • Page 271: Switching Of System Clock

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.3.4 Switching of System Clock Figure 6-13 shows the flow chart of the system clock switching (LSCLK à HSCLK). Oscillation only in low-speed clock 1.6 V ≤ V ＜1.8 V To (1) Voltage ≧...
  • Page 272 ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit Figure 6-14 shows the flow chart of the system clock switching (HSCLK à LSCLK). The state of both the low-speed clock and the high-speed clock are oscillating FCON=0x00 : When stopping the high-speed oscillation and switching...

  • Page 273: Switching Low-Speed Clock

    ML62Q1000 Series User's Manual Chapter 6 Clock Generation Circuit 6.3.5 Switching Low-speed clock Figure 6-15 shows a flow chart of the low-speed clock switching process (low-speed RC oscillation circuit à low-speed crystal oscillation circuit). Follow the flow chart below to check the state of the low-speed clock after releasing the STOP/STOP-D mode.

  • Page 274: Low Speed Time Base Counter

    Chapter 7 Low Speed Time Base Counter...

  • Page 275: General Description

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter Low Speed Time Base Counter 7.1 General Description The low speed time base counter enables following functions. ž Generate periodical interrupt requests ž Output periodical pulse signals to the general ports ž...

  • Page 276: Features

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.1.1 Features ML62Q1000 series common · Generate eight frequency (128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz and 1Hz) of pulse signals by dividing the low-speed clock (LSCLK) · Three interrupt requests can be chosen among eight periodical interrupt requests ·...

  • Page 277: Configuration

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.1.2 Configuration Figure 7-1 shows the configuration of the low speed time base counter on ML62Q1300 group. T128HZ LTBC2INT T64HZ T32HZ T16HZ LTBC1INT T8HZ T4HZ T2HZ LTBC0INT T1HZ (SA-ADC)
  • Page 278 ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter Figure 7-2 shows the configuration of the low speed time base counter on ML62Q1500 and ML62Q1700 group. T128HZ LTBC2INT T64HZ T32HZ T16HZ LTBC1INT T8HZ T4HZ T2HZ LTBC0INT T1HZ （SA-ADC）...

  • Page 279: List Of Pins

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.1.3 List of Pins The output pins of the low speed time base counter are assigned to the shared function of genral purpose ports. Signal name Function The virtual frequency adjustment clock output or the low speed time base...

  • Page 280: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.2 Description of Registers 7.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF060 Low-speed Time Base Counter register LTBR 0x00 0xF061 Reserved 0x00 0xF062 Low-speed Time Base Counter Control...

  • Page 281: Low Speed Time Base Counter Register (Ltbr)

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.2.2 Low Speed Time Base Counter Register (LTBR) The low speed time base counter register (LTBR) is a specific function register (SFR) to read the value of the time base counter.

  • Page 282: Low Speed Time Base Register Control Register (Ltbccon)

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.2.3 Low Speed Time Base Register Control Register (LTBCCON) The low speed time base counter control register (LTBCCON) is a specific function register (SFR) to control the function of the time base counter.

  • Page 283: Simplified Rtc Time Base Counter Register (Ltbrr)

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.2.4 Simplified RTC Time Base Counter register (LTBRR) The low speed time base counter register for Simplified RTC(LTBRR) is a specific function register (SFR) to read the counter value for the Simplified RTC.

  • Page 284: Low Speed Time Base Counter Frequency Adjustment Register (Ltbadj)

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.2.5 Low Speed Time base counter frequency adjustment register (LTBADJ) Time base counter frequency adjustment register (LTBADJ) is a specific function register (SFR) to set adjustment value for the frequency of time base clock.

  • Page 285: Low Speed Time Base Counter Interrupt Selection Register (Ltbint)

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.2.6 Low Speed Time Base Counter Interrupt Selection Register (LTBINT) The low speed time base counter interrupt selection register (LTBINT) is a specific function register (SFR) to specify the low-speed time base clock to be used as an interrupt signal.
  • Page 286 ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter [Note] Ÿ A time base counter interrupt may occur depending on a write timing to the LTBINTL or LTLBINTH. See the program example for initializing described in "7.3.1 Operation of the Low-speed Time Base Counter".

  • Page 287: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.3 Description of Operation 7.3.1 Low-speed Time Base Counter Operation The low-speed time base counter (LTBC) starts counting up from 0x0000 at the falling edge of the low-speed clock after releasing the system reset, then generates T128HZ to T1HZ signals.
  • Page 288 ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter Figure 7-5 shows the low-speed time base counter interrupt request generation timing when assigned to T128HZ, T16HZ, and T2HZ in the LTBINT register and the reset timing with writing to LTBR.

  • Page 289: Low Speed Time Base Counter Frequency Adjustment Function

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter 7.3.2 Low-speed Time Base Counter Frequency Adjustment Function For T8KHZ to T1HZ, T2HZR and T1HZR outputs of the low-speed time base counter, the frequency can be adjusted using the low-speed time base counter frequency adjustment register (LTBADJ).

  • Page 290: The Way Of Monitoring The Frequency On Lcd Drive Outputs

    ML62Q1000 Series User's Manual Chapter 7 Low Speed Time Base Counter Example 2: When adjusting -25.5 ppm (when the clock gains) Correction value = 25.5 ppm x 8388608 (decimal) = 25.5 x 10 x 8388608 = 213.909504 (decimal) ≈ D6h (hexadecimal) When setting LTBADJ, add a sign bit.
  • Page 291 Chapter 8 16-Bit Timer...

  • Page 292: 16-Bit Timer

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 16-Bit Timer 8.1 General Description The 16-bit timer enables following functions. ž Generate periodical interrupts in an arbitrary period ž Generate one shot interrupts in an arbitrary period ž Output pulse signals with an arbitrary frequency to the general ports ž...

  • Page 293: Features

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.1.1 Features · Two timer modes and two operation modes are available Timer mode Operation mode Description Count-able to the max. 0xffff Repeat mode Repeat the specified operation until stop by the software.

  • Page 294: Configuration

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.1.2 Configuration Figure 8-1 shows configuration of the 16-bit timer and Figure 8-2 shows configuration of the 8-bit timer SYSTEMCLK LSCLK Timer clock HSCLK Interrupt TMnINT control THnCS Timer control TMHnMD 16-bit Timer n...
  • Page 295 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.1.3 Lis of Pin The I/O pins of the 16-bit timer are assigned to the shared function of the general ports. Pin name Description EXI0 External clock input 0 EXI1 External clock input 01...

  • Page 296: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2 Description of Registers 8.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF300 TMH0DL 8/16 0xFF 16-bit timer 0 data register TMH0D 0xF301 TMH0DH 0xFF 0xF302 TMH1DL 8/16...
  • Page 297 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer Symbol Initial Address Name Size Value Byte Word 0xF32C TMH6MODL 8/16 0x00 16-bit timer 6 mode register TMH6MOD 0xF32D TMH6MODH 0x00 0xF32E TMH7MODL 8/16 0x00 16-bit timer 7 mode register TMH7MOD 0xF32F...

  • Page 298: 16-Bit Timer N Data Register (Tmhnd: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2.2 16-Bit Timer n Data Register (TMHnD: n = 0 to 7) TMHnD (n = 0 to 7) is a specific function register (SFR) to set the comparison value with the 16-bit timer n counter register (TMHnC).

  • Page 299: 16-Bit Timer N Counter Register (Tmhnc: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2.3 16-Bit Timer n Counter Register (TMHnC: n = 0 to 7) TMHnC (n = 0 to 7) is a specific function register (SFR) that functions as a 16-bit binary counter. The data in the TMHnC is counted up synchronizing at the riging edge of the timer clock.

  • Page 300: 16-Bit Timer N Mode Register (Tmhnmod: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2.4 16-Bit Timer n Mode Register (TMHnMOD: n = 0 to 7) TMHnMOD (n = 0 to 7) is a specific function register (SFR) to control the operation mode of 16-bit timer.
  • Page 301 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer clock chosen by the THnCS bit. Reserved bit THnCS This bit is used to choose the timer clock of the 16-bit timer n timer. 0: LSCLK (initial value) 1: HSCLK [Note] Ÿ...

  • Page 302: 16-Bit Timer N Interrupt Status Register (Tmhnis: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2.5 16-Bit Timer n Interrupt Status Register (TMHnIS: n = 0 to 7) TMHnIS is a specific function register (SFR) to indicate the status of the interrupt used in the 8-bit timer mode.

  • Page 303: 16-Bit Timer N Interrupt Clear Register (Tmhnic: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2.6 16-Bit Timer n Interrupt Clear Register (TMHnIC: n = 0 to 7) TMHnIC is a write-only specific function register (SFR) to clear the status of the interrupt used in the 8-bit timer mode.

  • Page 304: 16-Bit Timer Start Register (Tmhstr)

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2.7 16-Bit Timer Start Register (TMHSTR) TMHSTR is a specific function register (SFR) to control to start counting the 16-bit timer n. TMHSTRL is used in the 16-bit timer mode. TMHSTRH is used to start counting the upper side 8bit counter in the 8-bit timer mode.
  • Page 305 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer Bit symbol Bit no. Description name TH7RUN In the 16bit timer mode, controls the counter of 16bit timer 7 In the 8bit timer mode, controls the lower side 8bit counter of 16bit timer 7 Writing "0": Invalid...

  • Page 306: 16-Bit Timer Stop Register (Tmhstp)

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2.8 16-Bit Timer Stop Register (TMHSTP) TMHSTP is a specific function register (SFR) to control to stop counting the 16-bit timer n. TMHSTPL is used in the 16-bit timer mode. TMHSTPH is used to start counting the upper side 8bit counter in the 8-bit timer mode.
  • Page 307 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer Bit symbol Bit no. Description name TH7STP In the 16bit timer mode, controls the counter of 16bit timer 7 In the 8bit timer mode, controls the lower side 8bit counter of 16bit timer 7 Writing "0": Invalid...

  • Page 308: 16-Bit Timer Status Register (Tmhstat)

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.2.9 16-Bit Timer Status Register (TMHSTAT) TMHSTAT is a specific function register (SFR) to indicate the status of the 16-bit timer n. TMHSTATL is used in the 16-bit timer mode. TMHSTATH is fixed to 0 in the 16-bit timer mode.
  • Page 309 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer Bit symbol Bit no. Description name TH7STAT In the 16bit timer mode, indicates the status on the 16bit timer 7 In the 8bit timer mode, indicates the status on the lower side 8bit counter of 16bit timer 7...

  • Page 310: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3 Description of Operation Two timer modes are available for the 16-bit timer: ž 16-bit timer mode ž 8-bit timer mode 8.3.1 16-Bit Timer Mode When the THn8BM bit of the THnMOD register is set to "0", the timer operates in the 16-bit timer mode.
  • Page 311 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3.1.2 One-shot Mode Figure 8-4 shows the one-shot mode operation in the 16-bit timer mode. TMHnＣ register value Ｔ TMHnD register value TMHnSTAT TMHn Interrupt ＨｉＺ TMHnOUT Initial value Initial value The count...
  • Page 312 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3.1.3 Setting Example Figure 8-5 shows a setting example when using the 16-bit timer mode. Start High-speed clock Need when using the high-speed clock (HSCLK) for the timer clock setting Timer stop Confirm the corresponding bit of TMHSTAT register is “0”...

  • Page 313: 8-Bit Timer Mode

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3.2 8-Bit Timer Mode When the THn8BM bit of the THnMOD register is set to "1", the timer operates in the 8-bit timer mode. In the 8-bit timer mode, writing "1" to the THnHRUN bit causes the higher 8 bits (upper side 8-bit timer) of the 16-bit counter to start counting up in synchronization with the rising edges of the timer clock.
  • Page 314 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer The interrupt request TMnINT generation cycle and the port output variation cycle can be expressed in the following formula: TMHnDH + 1 (n=0 to 7) TMIH THnCK (Hz) TMHnDH : TMHnDH register setting value (0x01 to 0xFF)
  • Page 315 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3.2.2 One-shot Mode Figure 8-7 shows the operation waveforms in the one-shot mode. TMHnCH Ｔ TMHnDH setting value TMHnCL Ｔ TMHnDL setting value THnHSTAT THnLSTAT TMHnISH TMHnISL TMHn Interrupt ＨｉＺ Initial TMHnOUT...
  • Page 316 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3.2.3 Setting Example Figure 8-8 shows a setting example when using the 8-bit timer mode. Start High-speed clock Need when using the high-speed clock (HSCLK) for the timer clock setting Timer stop Confirm the corresponding bit of TMHSTAT register is “0”...
  • Page 317 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3.2.4 About Interrupt Request in 8-Bit Timer Mode In the 8-bit timer mode, the same interrupt requests (TMnINT) are used for the upper side 8-bit timer and the lower side 8-bit timer.

  • Page 318: Common Operation

    ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3.3 Common Operation 8.3.3.1 Start/Stop Timing Writing "1" to the THnRUN bit of the TMHSTR register causes the counting operation to start at the rising edge of the timer clock that follows.
  • Page 319 ML62Q1000 Series User's Manual Chapter 8 16-Bit Timer 8.3.3.2 External Input Count Timing If the external input is chosen for a count clock, counting up is executed through sampling the external input with the timer clock to detect a rising edge.

  • Page 320: Functional Timer

    Chapter 9 Functional Timer (FTM)

  • Page 321: General Description

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9. Functional Timer 9.1 General Description The Functional timer enables following functions in four operation modes (TIMER/CAPTURE/PWM1/PWM2). TIMER mode: In this mode, the MCU generates pulse signals reversed every timer cycle, changing the timer output level in syncroniztion with the count start or the over flow of the counter.
  • Page 322 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) The number of Functional timer channels is dependent of the product specification. Table 9-1 shows the number of channels. Table 9-1 Number of Functional Timer channels ML62Q1300 group ML62Q1500 / ML62Q1700 group...

  • Page 323: Features

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.1.1 Features · Enable the Timer/Capture/PWM functions using the 16-bit counter · For the count clock, 1 to 128 dividing of the LSCLK/HSCLK clock and the external trigger can be chosen ·...

  • Page 324: Configuration

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.1.2 Configuration Figure 9-1 shows the configuration of the FTM circuit. EXTRG0 or EXTRG4 can be chosen Emergency stop control FTMnTRG (FTM) FTMnTRG (FTM) TMH0TRG toTMH5TRG (16bit timer) Functional Timer n...

  • Page 325: List Of Pins

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.1.3 List of Pins The I/O pins of the Functional timer are assigned to the shared function of the general ports. Pin name Description EXTRG0 to External trigger n / External clock n...
  • Page 326 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Table 9-2 shows the list of the general ports used for the Functional timer and the register settings of the ports. Table 9-2 Ports used in the Functional timer and the register settings...

  • Page 327: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2 Description of Registers 9.2.1 List of Registers Symbol Initial Address Name Size value Byte Word 0xF400 FT0PL 8/16 0xFF FTM0 cycle register FT0P 0xF401 FT0PH 0xFF 0xF402 FT1PL 8/16 0xFF...
  • Page 328 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Symbol Initial Address Name Size value Byte Word 0xF42A FT5EBL 8/16 0x00 FTM5 event B register FT5EB 0xF42B FT5EBH 0x00 0xF42C FT6EBL 8/16 0x00 FTM6 event B register FT6EB 0xF42D FT6EBH...
  • Page 329 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Symbol Initial Address Name Size value Byte Word − 0xF458 FTM4 status register FT4STAT 0x30 − − 0xF459 Reserved 0x00 − 0xF45A FTM5 status register FT5STAT 0x30 − − 0xF45B Reserved 0x00 −...
  • Page 330 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Symbol Initial Address Name Size value Byte Word 0xF486 FT3TRG0L 8/16 0x00 FTM3 trigger register 0 FT3TRG0 0xF487 FT3TRG0H 0x00 0xF488 FT4TRG0L 8/16 0x00 FTM4 trigger register 0 FT4TRG0 0xF489 FT4TRG0H...
  • Page 331 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Symbol Initial Address Name Size value Byte Word 0xF4B4 FT2INTSL 8/16 0x00 FTM2 interrupt status register FT2INTS 0xF4B5 FT2INTSH 0x00 0xF4B6 FT3INTSL 8/16 0x00 FTM3 interrupt status register FT3INTS 0xF4B7 FT3INTSH...

  • Page 332: Ftmn Cycle Register (Ftnp: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.2 FTMn Cycle Register (FTnP: n = 0 to 7) FTnP is a specific function register (SFR) to set the cycle (clock count) of FTMn. The configurable range is 0x0001 to 0xFFFF (clock count: 2 to 65536).

  • Page 333: Ftmn Event Register A (Ftnea: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.3 FTMn Event Register A (FTnEA: n = 0 to 7) FTnEA is a specific function register (SFR) to set the event timing of FTMn or display the capture data. Set this register after setting the operation mode using FTnMD1 to 0 bits of FTnMOD register.

  • Page 334: Ftmn Event Register B (Ftneb: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.4 FTMn Event Register B (FTnEB: n = 0 to 7) FTnEB is a specific function register (SFR) to set the event timing of FTMn or display the capture data. Set this register after setting the operation mode using FTnMD1 to 0 bits of FTnMOD register.

  • Page 335: Ftmn Dead Time Register (Ftndt: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.5 FTMn Dead Time Register (FTnDT: n = 0 to 7) FTnDT is a specific function register (SFR) to set the dead time of timer output. Set this register after setting the operation mode using FTnMD1 to 0 bits of FTnMOD register.

  • Page 336: Ftmn Counter Register (Ftnc: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.6 FTMn Counter Register (FTnC: n = 0 to 7) FTnC is a specific function register (SFR) to display the counter value of FTMn. When writing to this register, the counter is cleared to "0x0000" in one clock of the timer clock.

  • Page 337: Ftmn Status Register (Ftnstat: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.7 FTMn Status Register (FTnSTAT: n = 0 to 7) FTnSTAT is a specific function register (SFR) to indicate the state of FTMn. Address: 0xF450(FT0STAT), 0xF452(FT1STAT), 0xF454(FT2STAT), 0xF456(FT3STAT), 0xF458(FT4STAT), 0xF45A(FT5STAT), 0xF45C(FT6STAT), 0xF45E(FT7STAT)

  • Page 338: Ftmn Mode Register (Ftnmod: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.8 FTMn Mode Register (FTnMOD: n = 0 to 7) FTnMOD is a specific function register (SFR) to set the FTMnP and FTMnN pin output function and the operation mode. The bit symbol "rsvd" means reserved bit. Write always "0" to those bits.
  • Page 339 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Bit symbol Bit no. Description name FTnOST This bit is used to set the repeat/one-shot mode of FTMn. Ÿ TIMER, PWM1, PWM2 mode Repeat mode (initial value) One-shot mode Ÿ CAPTURE mode...

  • Page 340: Ftmn Clock Register (Ftnclk: N=0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.9 FTMn Clock Register (FTnCLK: n=0 to 7) FTnCLK is a specific function register (SFR) to set the timer clock and count clock of the FTMn. The timer clock is used for sampling the external trigger input and for detecting the edge of the external clock input.
  • Page 341 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Bit symbol Bit no. Description name 2, 1 Reserved bit FTnCK0 This bit is used to choose the timer clock "FTnTCK" in the FTMn. LSCLK (Initial value) HSCLK [Note] Ÿ The pulse input to the EXTRG0 to EXTRG7 pin must have "the noise removal width chosen by FTnTRF2 to 0 bits of FTnTRG1 register + two timer clocks"...

  • Page 342: Ftmn Trigger Register 0 (Ftntrg0: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.10 FTMn Trigger Register 0 (FTnTRG0: n = 0 to 7) FTnTRG0 is a specific function register (SFR) to set the trigger function of FTMn. Address: 0xF480(FT0TRG0L/FT0TRG0), 0xF481(FT0TRG0H), 0xF482(FT1TRG0L/FT1TRG0), 0xF483(FT1TRG0H), 0xF484(FT2TRG0L/FT2TRG0), 0xF485(FT2TRG0H),...
  • Page 343 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Bit symbol Bit no. Description name 12 to 8 FTnSTSS, These bits are used to choose the trigger event source of FTMn. Choose a source except for FTnSTS3 to the interrupt target (e.g. do not choose the FTM0TRG when using the functional timer FTM0).
  • Page 344 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Bit symbol Bit no. Description name FTnSPC This bit is used to choose whether to enable clearing the counter when a trigger event for counter-stop occurs (only when the edge is chosen by the FTnTRM1-0 bits).

  • Page 345: Ftmn Trigger Register 1 (Ftntrg1: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.11 FTMn Trigger Register 1 (FTnTRG1: n = 0 to 7) FTnTRG1 is a specific function register (SFR) to set the trigger function of FTMn. Address: 0xF490(FT0TRG1L/FT0TRG1), 0xF491(FT0TRG1H), 0xF492(FT1TRG1L/FT1TRG1), 0xF493(FT1TRG1H), 0xF494(FT2TRG1L/FT2TRG1), 0xF495(FT2TRG1H),...
  • Page 346 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Bit symbol Bit no. Description name 2 to 0 FTnTRM2 to These bits are used to choose the edge or the level of the trigger event of FTMn. FTnTRM0 These are enabled only when EXTRG0-7 or CMP0D is chosen for the event trigger source. In other cases, it is fixed to the rising edge.

  • Page 347: Ftmn Interrupt Enable Register (Ftninte: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.12 FTMn Interrupt Enable Register (FTnINTE: n = 0 to 7) FTnINTE is a specific function register (SFR) to control the interrupt and trigger output of FTMn. When each bit of FTnINTEL is set to "1", the interrupt is enabled and notified to the interrupt controller.
  • Page 348 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Bit symbol Bit no. Description name FTnIEB This bit is used to enable the event timing B interrupt (in TIMER and PWM1 mode) or the capture B interrupt (in CAPTURE mode).

  • Page 349: Ftmn Interrupt Status Register (Ftnints: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.13 FTMn Interrupt Status Register (FTnINTS: n = 0 to 7) FTnINTS is a specific function register (SFR) to indicate the interrupt status of FTMn. The bit5 to bit0 is reset to "0" by writing "1" to the same number of bit in the MCINTCL register.
  • Page 350 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) Bit symbol Bit no. Description name FTnISA This is a bit to indicate the state of the event timing A interrupt of FTMn. In CAPTURE mode, it indicates the status of storing the capture data into the FTnEA register.

  • Page 351: Ftmn Interrupt Clear Register (Ftnintc: N = 0 To 7)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.14 FTMn Interrupt Clear Register (FTnINTC: n = 0 to 7) FTnINTC is a specific function register (SFR) to clear the interrupt status of FTMn. If the bit5 to bit0 is set to "1", the interrupt request indicated by the same number of bit in the FTnINTS register gets cleared.

  • Page 352: Ftm Common Update Register (Ftcud)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.15 FTM Common Update Register (FTCUD) FTCUD is a specific function register (SFR) to update FTnP, FTnEA, FTnEB and FTnDT registers while they are running. The FTCUD is an common SFR to each channel. The bit n corresponds to channel n.

  • Page 353: Ftm Common Control Register (Ftccon)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.16 FTM Common Control Register (FTCCON) FTCCON is a specific function register (SFR) to set the function of FTMn. The FTCCON is an common SFR to each channel. The bit n corresponds to channel n.

  • Page 354: Ftm Common Start Register (Ftcstr)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.17 FTM Common Start Register (FTCSTR) FTCSTR is a specific function register (SFR) to set the function of FTMn. This is an SFR common to each channel. Bit n corresponds to channel n.

  • Page 355: Ftm Common Stop Register (Ftcstp)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.18 FTM Common Stop Register (FTCSTP) FTCSTP is a specific function register (SFR) to set the function of FTMn. The FTCSTP is an common SFR to each channel. The bit n corresponds to channel n.

  • Page 356: Ftm Common Status Register (Ftcstat)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.2.19 FTM Common Status Register (FTCSTAT) FTCSTAT is a specific function register (SFR) to indicate the state of FTMn. The FTCSTAT is an common SFR to each channel. The bit n corresponds to channel n.

  • Page 357: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3 Description of Operation Four types of operation modes are available for the functional timer: · TIMER mode · CAPTURE mode · PWM1 mode · PWM2 mode 9.3.1 Common Sequence (Initial setting Common to All Modes) FTMn starts operating through the FTCSTR register after the setting via steps 1 through 6 described below is performed.
  • Page 358 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 6: Choice of the external output signal FTnOSL1 and FTnOSL0 bits of FTnMOD register are used to choose the positive output signal or negative phase output signal driven to the FTMnP pin or FTMnN pin.

  • Page 359: Counter Operation (Common To All Modes)

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.2 Counter Operation (Common to All Modes) The operation of FTM's internal counter is common to each mode. It counts up to the setting value of the FTnP register. In the repeat mode (the FTnOST bit of the FTnMOD register is "0"), the counter is cleared at the time of overflow, then continues the counting operation again.

  • Page 360: Timer Mode Operation

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.3 TIMER Mode Operation The TIMER mode controls the interrupt generation and output signal using the counter overflow. 9.3.3.1 Output Waveform in TIMER Mode The timer output has two kinds of phase, the positive phase and the negative phase.
  • Page 361 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnOSL1 and FTnOSL0 bits of FTnMOD register are used to choose the phase of the output signal driven to the FTMnP/FMnN pins. FTnOSNP bit is for reversing the output to the FTMnP pin. FTnOSNN bit is for reversing the output to the FTMnN pin.
  • Page 362 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnP Counter FTnSTA " " " " ●FTnOSNN= ; FTnOSNP= FTMnP (Positive phase, No reverse) FTMnN (Negative phase, No reverse) " " " " ●FTnOSNN= ; FTnOSNP= (Positive phase, Reverse) FTMnP...
  • Page 363 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnSTPO bit of FTnMOD register is used to choose output conditions when the counter stops. Figure 9-5(a) shows output waveforms when the FTnSTPO bit of the FTnMOD register is " ".

  • Page 364: Capture Mode Operation

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.4 CAPTURE Mode Operation The CAPTURE mode stores the count value, which was obtained when an event trigger source was generated, in the FTnEA or FTnEB register. The event trigger source for the capture is common to that used for counter start/stop.
  • Page 365 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) This is an exmaple for measuring the cycle and duty of the PWM signal input from the P02/EXTRG0 pin by the start/stop of a trigger event. Configure registers as follows before the measurment.
  • Page 366 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) In addition, the operation following the capturing is depending on the setting value in the FTnOST bit of the FTnMOD register. - In the auto mode (FTnOST=0) The value of the FTnEA register is updated when the counter is restarted with the the signal rising again.

  • Page 367: Pwm1 Mode Operation

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.5 PWM1 Mode Operation The PWM1 mode generates a pulse with the cycle set in the FTnP register. The duty of the Positive phase output is set in the FTnEA register and that of the Negative phase output is set in the FTnEB register.
  • Page 368 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnOSL1 and FTnOSL0 bits of FTnMOD register are used to choose the phase of the output signal driven to the FTMnP/FMnN pins. FTnOSNP bit is for reversing the output to the FTMnP pin. FTnOSNN bit is for reversing the output to the FTMnN pin.
  • Page 369 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnP FTnEA Counter FTnEB FTnSTR " " " " ●FTnOSNN= , FTnOSNP= (Positive phase, No reverse) FTMnP (Negative phase, No reverse) FTMnN " " " " ●FTnOSNN= , FTnOSNP= (Positive phase, Reverse)
  • Page 370 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnSTPO bit of FTnMOD register is used to choose output conditions when the counter stops. Figure 9-11(a) shows output waveforms when the FTnSTPO bit of the FTnMOD register is " ".

  • Page 371: Pwm2 Mode Operation

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.6 PWM2 Mode Operation PWM2 mode generates a complementary output pulse with the cycle set in the FTnP register. The duty of the Positive/Negative phase output is set in the FTnEA register. The FTnEB register is not used.
  • Page 372 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnOSL1 and FTnOSL0 bits of FTnMOD register are used to choose the phase of the output signal driven to the FTMnP/FMnN pins. FTnOSNP bit is for reversing the output to the FTMnP pin. FTnOSNN bit is for reversing the output to the FTMnN pin.
  • Page 373 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnP FTnEA Counter FTnSTR " " " " ●FTnOSNN= , FTnOSNP= FTMnP (Positive phase, No reverse) (Negative phase, No reverse) FTMnN " " " " ●FTnOSNN= , FTnOSNP= (Positive phase, Reverse)
  • Page 374 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnSTPO bit of FTnMOD register is used to choose output conditions when the counter stops. Figure 9-14(a) shows output waveforms when the FTnSTPO bit of the FTnMOD register is " ".

  • Page 375: Event Trigger/Emergency Stop Trigger Control

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.7 Event Trigger/Emergency Stop Trigger Control 9.3.7.1 Trigger Signal The functional timer can accept two types of trigger signal: event trigger and emergency stop trigger. The event trigger is used as counter start/stop or trigger for capture.
  • Page 376 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.7.2 Start/Stop Operations by Event Trigger Here is the setting used to control the counter by event triggers. First, before controlling the counter, set the following configuration by FTnTRG0 and FTnTRG1 registers.
  • Page 377 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.7.3 Emergency Stop Operation Writing "1" to the FTnEMGEN bit of the FTCCON register causes the emergency stop function to be enabled. Set the FTnEMGEN bit after the trigger source is chosen in the FTnEST bit of the FTnTRG0 register.

  • Page 378: Output At Counter Stop

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.8 Output at Counter Stop The state of Positive/Negative phase output when the counter is stopped by the software control or the event trigger input is determined by the FTnSTPO bit setting of the FTnMOD register.

  • Page 379: Changing Cycle, Event A/B, And Dead Time During Operation

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.9 Changing Cycle, Event A/B, and Dead Time during Operation The cycle, event A/B, and dead time can be updated by setting FTnP/ FTnEA/ FTnEB/ FTnDT registers. The update timing is depending on the counter operation status and the counter value when writing data to the registers.
  • Page 380 ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) FTnRUN Buffer for cycle Buffer for cycle Buffer for event B Counter Buffer for event A Buffer for event A Buffer for event B Buffer for dead time Buffer for dead time...

  • Page 381: Interrupt Source

    ML62Q1000 Series User's Manual Chapter 9 Functional Timer (FTM) 9.3.10 Interrupt Source This section describes the interrupt source and how to clear it. Writing "1" to the corresponding bit (FTnIE*) of the FTnINTE register causes each interrupt request to be enabled.

  • Page 382: Watchdog Timer

    Chapter 10 Watchdog Timer...

  • Page 383: General Description

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10. Watchdog Timer 10.1 General Description The watchdog timer (WDT) is equipped with the following functions and can detect the runaway state of program or the undefined state of the CPU by generating an interrupt or reset when an abnormality occurs.

  • Page 384: Features

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.1.1 Features · Eight types of overflow periods can be chosen (7.8 ms, 15.6 ms, 31.3 ms, 62.5 ms, 125 ms, 500 ms, 2 s, or 8 s) · Two types of use are available: ・...

  • Page 385: Configuration

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.1.2 Configuration The following diagram shows the configuration of the watchdog timer. Clock generation circuit WDTNMCK (code option) RC1K WDT overflow WDTCLK 1/32 LSCLK WDT counter WDT interrupt (32 dividing) (WDTINT) Reset...

  • Page 386: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.2 Description of Registers 10.2.1 List of Registers Symbol name Initial Address Name Size value byte Word 0xF010 Watchdog timer control register WDTCON 0x00 0xF011 Reserved register 0x00 0xF012 Watchdog timer mode register...

  • Page 387: Watchdog Timer Control Register (Wdtcon)

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.2.2 Watchdog timer control register (WDTCON) This register is a special function register (SFR) to clear the WDT counter. Address: 0xF010 Access: Access size: 8 bit Initial value: 0x00 Word Byte WDTCON...

  • Page 388: Watchdog Timer Mode Register (Wdtmod)

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.2.3 Watchdog Timer Mode Register (WDTMOD) This register is a special function register (SFR) to set the overflow period and the clear enabled period of the WDT counter. Address: 0xF012 Access: Access size: 8 bit...

  • Page 389: Watchdog Timer Counter Register (Wdtmc)

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.2.4 Watchdog Timer Counter Register (WDTMC) This register is a read-only special function register (SFR) to read the WDT counter value. Address: 0xF014 Access: Access size: 8/16 bits Initial value: 0x0000 Word...

  • Page 390: Watchdog Status Register (Wdtsta)

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.2.5 Watchdog Status Register (WDTSTA) This register is a read-only special function register (SFR) to indicate the WDT counter clearing state. Address: 0xF016 Access: Access size: 8 bit Initial value: 0x01 Word...

  • Page 391: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.3 Description of Operation The WDT counter starts counting up at the rising edge of the WDT counter operation clock (WDTCLK) chosen by the code option when the system reset is released with operation enabled also by the code option.

  • Page 392: How To Clear Wdt Counter

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.3.1 How to Clear WDT Counter The WDT counter can be cleared by writing "0x5A" to the WDTCON register with the WDP bit set to "0", then writing "0xA5" to the WDTCON register with the WDP bit set to "1" while WDT counter clearing is enabled.
  • Page 393 ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer [Note] Ÿ Maximum of two clocks of WDTCLK are required during the period between writing "0x5A", "0xA5" to the WDTCON register and clearing of the WDT counter. To enter the STOP mode or STOP-D mode following WDT clearing, do so after making sure that the WDTCLR1 bit became "0".

  • Page 394: Window Function Disabled Mode

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.3.2 Window Function Disabled Mode In the window function disabled mode, if the WDT counter is uncleared within the WDT counter overflow period (T and the counter overflows for the first time, a WDT interrupt is generated. If the WDT counter is not cleared even by the software processing after the WDT interrupt, and overflows again, a WDT reset occurs.
  • Page 395 ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer The following figure shows an operation timing overview of the window function disabled mode WDT counter value Overflow period (T Time WDT cleared WDT interrupt generated Clear enabled period (T Overflow period...
  • Page 396 ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer WDT counter value Overflow period (T Time WDT cleared WDT cleared interrupt generated reset generated (enabled) (disabled) 7999 ms 7998 ms 8000 ms 8000 ms The clear processing is enable for two clocks of the WDTCLK (2ms when the WDTCLK is 1.024kHz) before the WDT gets overflowed.
  • Page 397 ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer The following figure shows details of operation timing in the window function disabled mode. WDT clock Program start oscillation starts Occurrence (2) WDTMOD RESET_N WDTMOD setting setting system reset 5A A5 Data:...

  • Page 398: Window Function Enabled Mode

    ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer 10.3.3 Window Function Enabled Mode In the window function enabled mode, if the WDT counter is uncleared within the WDT clear enabled period and the counter overflows first time, the WDT reset is generated.
  • Page 399 ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer Overviews of the operation of each mode are shown below. WDT counter value Overflow period (T Time WDT counter clear 75% for clear enabled period 25% for clear disabled period Overflow period...
  • Page 400 ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer The following table shows WDT counter clear enabled periods. If the overflow period of the WDT counter is set to 62.5 ms or less in WDT2 to 0 bits, the window function is disabled regardless of setting values of WOVF1 and WOVF0 bits.
  • Page 401 ML62Q1000 Series User's Manual Chapter 10 Watchdog Timer The following figure shows details of operation timing in the window function enabled mode. WDT clock oscillation starts Program start (6) Error occurs RESET_N (2) WDTMOD WDTMOD setting setting System reset WDTCON register...

  • Page 402: Serial Communication Unit

    Chapter 11 Serial Communication Unit...

  • Page 403: General Description

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11. Serial Communication Unit 11.1 General Description ML62Q1000 Sereis has two types of the serial communication function: Ÿ 8-bit/16-bit synchronous serial port (SSIO) Ÿ Asynchronous serial interface UART (Universal Asynchronous Receiver Transmitter) The number of serial communication unit channels is dependent of the product specification.

  • Page 404: Features

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.1.1 Features Two serial communication modes are available. Table 11-2 shows feagures of the serial communication. Table 11-2 Features of the Serial Communication Serial Commnication mode Operation mode Features ・ Max. 6ch (Both SSIO and UART are unavailable to use in the...

  • Page 405: Configuration

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.1.2 Configuration Figure 11-1 shows configuration of the serial communication unit. SUn_SCLK SUn_RXD0/1 SUn_SIN Shift register SUn_TXD0/1 8/16bits (SSIO) Clock SUn_SOUT 5/6/7/8bits (UART) Dividing Circuit SUn_SCLK Baud rate LSCLK generator HSCLK...

  • Page 406: List Of Pins

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.1.3 List of Pins The I/O pins of the serial communication unit are assigned to the shared function of the general ports. For details about the pin assignment and the shared function of genral ports, see Chapter 17 "GPIO."...
  • Page 407 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Table 11-3 (1) and (2) show the list of the general ports used for the serial communication unit and the register settings of the ports. Table 11-3(1) Ports used for the serial communication unit and the register settings (UART)
  • Page 408 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit ML62Q1500 ML62Q1300 ML62Q1700 group group Setting Pin name Shared port Setting value register ● ● Func. P8MOD1 0001_XXXX SU4_TXD0 ● ● Func. P9MOD4 0001_XXXX ● ● Func. P4MOD4 0010_XXXX ● ●...
  • Page 409 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Table 11-3(2) Ports used in the serial communication unit and the register settings (SSIO) ML62Q1500 ML62Q1300 ML62Q1700 group group Setting Pin name Shared port Setting value register ● ● ● ●...

  • Page 410: Combination Of Ssio Port

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit “XXXX” determines the condition of the port output XXXX Condition of the port output 0010 CMOS output (SSIO master mode) 0001 Input (SSIO slave mode) 11.1.4 Combination of SSIO port SUn_SIN, SUn_SOUT and SUn_SCLK are assigned to multiple general ports.

  • Page 411: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2 Description of Registers 11.2.1 List of Registers Symbol Initial Address Name Size value Byte Word 0xF600 SD0BUFL 8/16 0x00 Serial communication unit 0 SD0BUF transmission/reception buffer 0xF601 SD0BUFH 0x00 −...
  • Page 412 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Symbol Address Initial Name Size value Byte Word 0xF620 SD1BUFL 8/16 0x00 Serial communication unit 1 SD1BUF transmission/reception buffer 0xF621 SD1BUFH 0x00 − 0xF622 Serial communication unit 1 mode register SU1MOD 0x00 −...
  • Page 413 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Symbol Address Initial Name Size value Byte Word 0xF640 SD2BUFL 8/16 0x00 Serial communication unit 2 SD2BUF transmission/reception buffer 0xF641 SD2BUFH 0x00 − 0xF642 Serial communication unit 2 mode register SU2MOD 0x00 −...
  • Page 414 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Symbol Address Initial Name Size value Byte Word 0xF660 SD3BUFL 8/16 0x00 Serial communication unit 3 SD3BUF transmission/reception buffer 0xF661 SD3BUFH 0x00 − 0xF662 Serial communication unit 3 mode register SU3MOD 0x00 −...
  • Page 415 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Symbol Address Initial Name Size value Byte Word 0xF680 SD4BUFL 8/16 0x00 Serial communication unit 4 SD4BUF transmission/reception buffer 0xF681 SD4BUFH 0x00 − 0xF682 Serial communication unit 4 mode register SU4MOD 0x00 −...
  • Page 416 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Symbol Address Initial Name Size value Byte Word 0xF6A0 SD5BUFL 8/16 0x00 Serial communication unit 5 SD5BUF transmission/reception buffer 0xF6A1 SD5BUFH 0x00 − 0xF6A2 Serial communication unit 5 mode register SU5MOD 0x00 −...
  • Page 417 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Table 11-4 shows lists of the specific function register (SFR), the communication pin and the interrupt used in each mode. The communication mode is chosen by the SUnMD1 bit and SUnMD0 bit of SUnMOD register.

  • Page 418: Serial Communication Unit N Transmit/Receive Buffer (Sdnbuf)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.2 Serial Communication Unit n Transmit/Receive Buffer (SDnBUF) SDnBUF is a specific function register (SFR) to store transmission/ reception data of the serial communication unit. Address: 0xF600(SD0BUFL/SD0BUF), 0xF601(SD0BUFH), 0xF620(SD1BUFL/SD1BUF), 0xF621(SD1BUFH), 0xF640(SD2BUFL/SD2BUF), 0xF641(SD2BUFH),...
  • Page 419 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Ÿ Synchronous Serial I/O (SSIO) port mode If writing a data to the SDnBUF register, it also written to the transmission register (SUnTR). If reading the SDnBUF register, data in the reception register (SUnRC) is read out.

  • Page 420: Serial Communication Unit N Mode Register (Sunmod)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.3 Serial Communication Unit n Mode Register (SUnMOD) SUnMOD is a specific function register (SFR) to choose the communication mode of the serial communication unit. Address: 0xF602(SU0MOD), 0xF622(SU1MOD), 0xF642(SU2MOD), 0xF662(SU3MOD), 0xF682(SU4MOD), 0xF6A2(SU5MOD)

  • Page 421: Serial Communication Unit N Transmission Interval Setting Register (Sundly)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.4 Serial Communication Unit n Transmission Interval Setting Register (SUnDLY) SUnDLY is a specific function register (SFR) to set the transmission frame interval of serial communication. It is used for the slave device to wait for a data reception process when continuously transmitting the serial data.
  • Page 422 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit SSIO mode SUnMOD SIOnMOD Base clock SUnMD1 SUnMD0 SnCK4 SnCK3 SnCK2 SnCK1 LSCLK (Initial value) HSCLK UART mode SUnMOD UAnMOD Base clock SUnMD1 SUnMD0 UnCK1 LSCLK HSCLK LSCLK HSCLK [Note] Ÿ...

  • Page 423: Serial Communication Unit N Control Register (Suncon)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.5 Serial Communication Unit n Control Register (SUnCON) SUnCON is a specific function register (SFR) to control the serial communication unit. Address: 0xF606(SU0CONL/SU0CON), 0xF607(SU0CONH), 0xF626(SU1CONL/SU1CON), 0xF627(SU1CONH), 0xF646(SU2CONL/SU2CON), 0xF647(SU2CONH), 0xF666(SU3CONL/SU3CON), 0xF667(SU3CONH), 0xF686(SU4CONL/SU4CON),...

  • Page 424: Synchronous Serial Port N Mode Register (Sionmod)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.6 Synchronous Serial Port n Mode Register (SIOnMOD) SIOnMOD is a specific function register (SFR) to set the communication mode of the SSIO port. Address: 0xF608(SIO0MODL/SIO0MOD), 0xF609(SIO0MODH), 0xF628(SIO1MODL/SIO1MOD), 0xF629(SIO1MODH), 0xF648(SIO2MODL/SIO2MOD), 0xF649(SIO2MODH),...
  • Page 425 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Bit symbol Bit no. Description name 7 to 4 Reserved bit SnLG This bit is used choose the bit length of the transmission/reception data in the SSIO mode. 8-bit length (initial value)

  • Page 426: Synchronous Serial Port N Status Register (Sionstat)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.7 Synchronous Serial Port n Status Register (SIOnSTAT) SIOnSTAT is s specific function register (SFR) to indicate the state of the transmission/reception operation in the SSIO mode. Address: 0xF60A(SIO0STAT), 0xF62A(SIO1STAT), 0xF64A(SIO2STAT), 0xF66A(SIO3STAT),...
  • Page 427 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Bit symbol Bit no. Description name SnTUER This bit is used to indicate a transmission underrun error. If writing a data to SDnBUF register when the SnFUL bit is “0”, the SnTUER bit is set to “1”.

  • Page 428: Uartn0 Mode Register (Uan0Mod)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.8 UARTn0 Mode Register (UAn0MOD) UAn0MOD is a specific function register (SFR) to set the mode in UARTn0 full-duplex communiction mode and half-duplex communication mode. Address: 0xF60C(UA00MODL/UA00CON), 0xF60D(UA00MODH), 0xF62C(UA10MODL/UA10MOD), 0xF62D(UA10MODH), 0xF64C(UA20MODL/UA20CON), 0xF64D(UA20MODH),...
  • Page 429 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Bit symbol Bit no. Description name Un0RSS This bit is used to choose sampling timing of the reception data in UARTn0 full-duplex and half-duplex mode. (Values set to UAn0BRTH and UAn0BRTL registers)/2 (initial value)

  • Page 430: Uartn1 Mode Register (Uan1Mod)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.9 UARTn1 Mode Register (UAn1MOD) UAn1MOD is a specific function register (SFR) to set the transfer mode in UARTn1 half-duplex communication mode. When the full-duplex communication is chosen, no need to specify this register.
  • Page 431 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Bit symbol Bit no. Description name Un1RSS This bit is used to choose the sampling timing of the reception data in UARTn1 half-duplex mode. (Values set to UAn1BRTH and UAn1BRTL registers)/2 (initial value)

  • Page 432: Uartn0 Baud Rate Register (Uan0Brt)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.10 UARTn0 Baud Rate Register (UAn0BRT) UAn0BRT is a specific function register (SFR) to set the count value of the baud rate generator in UARTn0 full-duplex communiction mode and half-duplex communication mode.

  • Page 433: Uartn0 Baud Rate Adjustment Register (Uan0Brc)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.12 UARTn0 Baud Rate Adjustment Register (UAn0BRC) UAn0BRC is a specific function register (SFR) to adjust the count value of the baud rate generator in UARTn0 full-duplex communiction mode and half-duplex communication mode.

  • Page 434: Uartn0 Status Register (Uan0Stat)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.14 UARTn0 Status Register (UAn0STAT) UAn0STAT is a specific function register (SFR) to indicate the state in the transmit/receive operation in UARTn0 full-duplex communiction mode and half-duplex communication mode. Address: 0xF612(UA00STAT), 0xF632(UA10STAT), 0xF652(UA20STAT), 0xF672(UA30STAT),...
  • Page 435 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Bit symbol Bit no. Description name Un0OER This bit is used to indicate an overrun error in UARTn0 full-duplex communication mode and half-duplex communication mode. This bit becomes "1" if the next data is received before reading the previous receive data in the serial communication unit n transmit/receive buffer L (SDnBUFL).

  • Page 436: Uartn1 Status Register (Uan1Stat)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.2.15 UARTn1 Status Register (UAn1STAT) UAn1STAT is a specific function register (SFR) to indicate the state in the transmit/receive operation in UARTn1 half-duplex communication mode. When the full-duplex communication mode is chosen, the contents of the UAn1STAT register is invalid.
  • Page 437 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Bit symbol Bit no. Description name Un1OER This bit is used to indicate an overrun error in UARTn1 half-duplex communication mode. This bit becomes "1" if the next data is received before reading the previous receive data in the serial communication unit n transmit/receive buffer H (SDnBUFH).

  • Page 438: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3 Description of Operation 11.3.1 Synchronous Serial Port (SSIO) 11.3.1.1 Transmit Operation Timing Figure 11-2 shows the transmission operation waveform (with 8-bit length, LSB first) of the synchronous serial port for clock type 0 (positive logic).
  • Page 439 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit SnEN SUn_SCLK SDnBUF Transmit data SUn_SOUT SIUn0INT When an interrupt at the end of transmission is set SnFUL SnTXF Figure 11-5 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 (Negative Logic)
  • Page 440 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.1.2 Receive Operation Timing Figure 11-6 shows the reception operation waveform (with 8-bit length, MSB first) of the synchronous serial port for clock type 0 (positive logic). Figure 11-7 shows the one for clock type 0 (negative logic), Figure 11-8 the one for clock type 1 (positive logic), and Figure 11-9 the one for clock type 1 (negative logic).
  • Page 441 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit SnEN SUn_SCLK SUn_SIN Shift register SUnRC0 Receive data When an interrupt at the start of reception is set SIUn0INT Write SDnBUF When an interrupt at the end of reception is set...
  • Page 442 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.1.3 Transmit/Receive Operation Timing Figure 11-10 shows the transmission/reception operation waveform (with 16-bit length, LSB first, clock type 0) of the synchronous serial port. SnEN SUn_SCLK Transmit data SDnBUF SUn_SOUT SUn_SIN...
  • Page 443 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.1.4 Interrupt Generation Timing Table 11-5 shows the interrupt generation timing in the synchronous serial port mode. Table 11-5 Interrupt Generation Timing in Synchronous Serial Port Mode (1/2) Master mode Setting of Setting of Interrupt Timing of the interrupt generation ("|"...
  • Page 444 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Table 11-5 Interrupt Generation Timing in Synchronous Serial Port Mode (2/2) n Slave mode Setting of Setting of Interrupt Timing of the interrupt generation ("|" indicates the interrupt） Operation mode transmission...
  • Page 445 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.1.5 DMA Request Timing Table 11-6 shows the DMA request timing in the synchronous serial port mode. Table 11-6 DMA Request Timing in Synchronous Serial Port Mode Master mode Setting of Operation Timing of the interrupt generation ("|"...
  • Page 446 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.1.6 Timing in Clock Type 1 Slave Mode The operation is fundamentally performed in the same timing in both the master and slave modes. In the clock type 1 slave mode, in order for it to be able to perform any time when the clock is supplied from the master, preparation for data transfer that follows is started as soon as the preceding data transfer is completed.

  • Page 447: Asynchronous Serial Interface (Uart)

    ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.2 Asynchronous Serial Interface (UART) 11.3.2.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, the following are chooseable: 5 to 8 bits for the data bit, availability of parity, even/odd parity, parity fixed to "1", or parity...
  • Page 448 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.2.2 Baud Rate The baud rate generator generates a baud rate using the base clock chosen in the UARTn mode register (UAn0MOD and UAn1MOD). The setting values for the UARTn baud rate register (UAn0BRT and UAn1BRT) and the UARTn baud rate adjustment register (UAn0BRC and UAn1BRC) can be calculated by the following formulae.
  • Page 449 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit Table 11-7 Count Values for Typical Baud Rates (2/2) UAn0BRT UAn0BRC Actual Base clock Baud rate UAn1BRT UAn1BRC baud rate (bps) 299.99bps 300bps 0xD035 0x05 1,200bps 0x340C 0x05 1200.00bps 2399.98bps 2,400bps...
  • Page 450 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.2.3 Direction of Transmit/Receive Data Figure 11-14 shows the relationship between the transmission/reception buffer and transmission/reception data. ● When the data length is 8-bit length LSB transmission LSB reception SnB7 SnB6...
  • Page 451 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.2.4 Transmit Operation The following shows the transmission procedure in the UART full-duplex communication mode. Figure 11-15 shows the operation timing for transmission. Ÿ To prepare the communication (settings common to transmission/reception for full-duplex communication): −...
  • Page 452 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.2.5 Receive Operation The following shows the reception procedure in the UART full-duplex communication mode. Figure 11-16 shows the operation timing for reception. Ÿ To prepare the communication (settings common to transmission/reception for full-duplex communication): −...
  • Page 453 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.2.6 Interrupt Generation Timing Table 11-8 shows the interrupt generation timing in the UART mode. Table 11-8 Interrupt Generation Timing in UART Mode Setting of Operation Timing of the interrupt generation ("|" indicates the interrupt）...
  • Page 454 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.2.8 Detection of Start Bit The start bit is sampled with the baud rate generator base clock. Therefore, the start bit detection may be delayed for one cycle of the baud rate generator clock at the maximum.
  • Page 455 ML62Q1000 Series User's Manual Chapter 11 Serial Communication Unit 11.3.2.10 Receive Margin If there is an error between the sender baud rate and the receiver baud rate generated by the baud rate generator, the error accumulates until the last stop bit loading in one frame, decreasing the reception margin.
  • Page 456 Chapter 12 I C Bus Unit...

  • Page 457: I2C Bus Unit

    C Bus Unit 12.1 General Description ML62Q1000 series has one channel of I C bus unit that supports both master and slave function. Either of master or slave can be chosen to use and both functions of master and slave are unworkable at the same time.

  • Page 458: Configuration

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.1.2 Configuration Figure 12-1 shows the configuration diagram of the I C bus unit circuit. Master I2UM0RD, I2UM0STA I2CU0_SCL pin Controller Clock HSCLK Shift register Generation LSCLK I2CU0_SDA pin Circuit Controller...

  • Page 459: Pin Setting

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.1.3 List of Pins The I/O pins of the I C bus unit are assigned to the shared function of the general ports. For details about the pin assignment and the shared function of genral ports, see Chapter 17 "GPIO."...
  • Page 460 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2 Description of Registers 12.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF6C0 C bus unit 0 mode register I2U0MSS 0x00 0xF6C1 Reserved 0x00 0xF6C2 C bus 0 receive register (master)

  • Page 461: I2C Bus Unit 0 Mode Register (I2U0Mss)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.2 I C Bus Unit 0 Mode Register (I2U0MSS) I2U0MD is a special function register (SFR) used to choose the Master mode or Slave mode of the I C bus unit.

  • Page 462: I2C Bus 0 Receive Register (Master) (I2Um0Rd)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.3 I C Bus 0 Receive Register (Master) (I2UM0RD) I2UM0RD is a read-only special function register (SFR) used to store the received data in the master mode. The I2UM0RD is updated after completion of each reception.

  • Page 463: I2C Bus 0 Slave Address Register (Master) (I2Um0Sa)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.4 I C Bus 0 Slave Address Register (Master) (I2UM0SA) I2UM0SA is a special function register (SFR) to set the address and transmission/reception mode of the slave device in master mode.

  • Page 464: I2C Bus 0 Transmit Data Register (Master) (I2Um0Td)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.5 I C Bus 0 Transmit Data Register (Master) (I2UM0TD) I2UM0TD is a special function register (SFR) used to set the transmission data in the master mode. Address: 0xF6C6 (I2UM0TD) Access:...

  • Page 465: I2C Bus 0 Control Register (Master) (I2Um0Con)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.6 I C Bus 0 Control Register (Master) (I2UM0CON) I2UM0CON is a special function register (SFR) used to control transmission and reception operations in the master mode. Address: 0xF6C8 (I2UM0CON) Access:...

  • Page 466: I2C Bus 0 Mode Register (Master) (I2Um0Mod)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.7 I C Bus 0 Mode Register (Master) (I2UM0MOD) I2UM0MOD is a special function register (SFR) used to set the operation mode in the master mode. Address: 0xF6CA (I2UM0MDL/I2UM0MOD)，0xF6CB (I2UM0MDH) Access:...
  • Page 467 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit Bit symbol Bit no. Description name I2UM0EN This bit is used to enable the master operation. When "1" is written to this bit, the I2UM0ST bit can be set and the I2UM0BB bit starts operation. When "0" is written to this bit, the I2C master stops operation and the I2UM0RD, I2UM0SA, I2UM0TD and I2UM0CON registers are initialized.

  • Page 468: I2C Bus 0 Status Register (Master) (I2Um0Str)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.8 I C Bus 0 Status Register (Master) (I2UM0STR) I2UM0STR is a special function register (SFR) to indicate the state of the I C bus unit in the master mode. Address: 0xF6CC (I2UM0STA/I2UM0STR)，0xF6CD (I2UM0ISR)
  • Page 469 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit Bit symbol Bit no. Description name Even if this bit is set to "1", the I2CU0_SDA pin output continues until the subsequent byte data communication terminates when the clock stretch function is not used (I2UM0SYN = "0").

  • Page 470: I2C Bus 0 Receive Register (Slave) (I2Us0Rd)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.9 I C Bus 0 Receive Register (Slave) (I2US0RD) I2US0RD is a read-only special function register (SFR) used to store the received data in the slave mode. The I2US0RD is updated after completion of each reception.

  • Page 471: I2C Bus 0 Slave Address Register (Slave) (I2Us0Sa)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.10 I C Bus 0 Slave Address Register (Slave) (I2US0SA) I2US0SA is a special function register (SFR) used to set the slave address in the slave mode. Address: 0xF6D0 (I2US0SA) Access:...

  • Page 472: I2C Bus 0 Transmit Data Register (Slave) (I2Us0Td)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.11 I C Bus 0 Transmit Data Register (Slave) (I2US0TD) I2US0TD is a special function register (SFR) used to set the transmission data in the slave mode. Address: 0xF6D2 (I2US0TD) Access:...

  • Page 473: I2C Bus 0 Control Register (Slave) (I2Us0Con)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.12 I C Bus 0 Control Register (Slave) (I2US0CON) I2US0CON is a special function register (SFR) used to control transmission and reception operations in the slave mode. Address: 0xF6D4 (I2US0CON) Access:...

  • Page 474: I2C Bus 0 Mode Register (Slave) (I2Us0Md)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.13 I C Bus 0 Mode Register (Slave) (I2US0MD) I2US0MD is a special function register (SFR) used to set the operation mode in the slave mode. Address: 0xF6D6 (I2US0MD) Access: Access size:...

  • Page 475: I2C Bus 0 Status Register (Slave) (I2Us0Sta)

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.2.14 I C Bus 0 Status Register (Slave) (I2US0STA) I2US0STA is a special function register (SFR) to indicate the state of the I C bus unit in the slave mode. Address: 0xF6D8 (I2US0STA/I2US0STR)，0xF6D9 (I2US0ISR)
  • Page 476 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit Bit symbol Bit no. Description name I2US0TR This bit is used to indicate the transmitting or receiving state in the slave mode. This bit is set to "1" when detecting the I2UM0RW bit of I2UM0SA register is "1" (data received mode).

  • Page 477: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3 Description of Operation 12.3.1 Master Operation The following flow charts describe procedures of each operation in the master mode. 12.3.1.1 Initial Setting of Communication Operation Initial setting start Confirm I2UM0ST=0 in the I2UM0CON register...
  • Page 478 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.1.3 Restart Condition Restart condition start Communication in progress (I2UM0ST=1) Set I2UM0RS=1 and I2UM0ST=1 in the I2UM0CON register Restart communication, start communication Output restart condition waveforms to I2CU0_SDA and I2CU0_SCL pins.
  • Page 479 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.1.5 Control Register Setting Wait State Control register setting wait state start Generate I C bus unit 0 interrupt When entering the control register setting wait state, (I2CU0INT) an interrupt is generated through hardware...
  • Page 480 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.1.7 Data Reception Mode Data receive mode start Value (received data) input to I2CU0_SDA pin Store each bit of received data is stored in synchronization with rising edge of in shift register (8-bit) one by one...

  • Page 481: Master Mode Communication Operation Timing

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.2 Master Mode Communication Operation Timing Figures 12-2 to 12-4 show the operation timing and control method for each communication mode during the master operation. Start Stop Restart condition condition condition Register I2UM0SA="xxxxxxx0B"...
  • Page 482 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit Figure 12-5 shows the operation timing and control method when an acknowledgment error occurs. Acknowledge error Register I2UM0SA="xxxxxxx0B" setting I2UM0CON="01H" I2UM0CON="02H" I2CU0_SDA pin Values of I2UM0SA I2CU0INT I2UM0ST bit I2UM0RD register...

  • Page 483: Slave Operation

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.3 Slave Operation The following flow charts describe procedures of each operation in the slave mode. 12.3.3.1 Initial Setting of Communication Operation Initial setting start Confirm I2UM0ST=0 in the I2UM0CON register...
  • Page 484 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.3.3 Slave Address Reception Mode Slave address receive mode Value (slave address, data direction bit) input to I2CU0_SDA pin Store each bit of received data is stored in synchronization with rising edge of...
  • Page 485 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.3.4 Communication Wait State Communication wait state start Generate I C bus unit interrupt When entering communication wait state, (I2CU0INT) an interrupt is generated through hardware Fix I2CU0_SCL pin to "L" level...
  • Page 486 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.3.6 Data Reception Mode Data receive mode start Value (received data) input to I2CU0_SDA pin Store each bit of received data is stored in synchronization with rising edge of in shift register (8-bit) one by one...

  • Page 487: Slave Mode Communication Operation Timing

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.4 Slave Mode Communication Operation Timing Figures 12-7 to 12-9 show the operation timing and control method for each communication mode. Start Stop Restart condition condition condition Register setting I2US0CON="20H" I2US0CON="20H" I2US0CON="20H"...
  • Page 488 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit When the values of the transmitted bit and the I2CU0_SDA pin do not coincide, the I2US0ER bit of the I C bus 0 status register (I2US0STA) is set to "1" and the I2CU0_SDA pin output is disabled until termination of the subsequent byte data communication.

  • Page 489: Operation Waveforms

    ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit 12.3.5 Operation Waveforms Figure 12-11 shows the operation waveforms of I2CU0_SDA and I2CU0_SCL pins and the I2UM0BB flag of the I2UM0STA register. Table 12-4 and 12-5 show the relationship between communication speeds and HSCLK clock counts.
  • Page 490 ML62Q1000 Series User's Manual Chapter 12 I2C Bus Unit Table 12-5 Relationship between Communication Speeds and HSCLK Clock Counts (at HSCLK=16MHz) I2UM0MOD register Communication Speed reduction speed HD:STA HD:DAT HIGH SU:STA SU:DAT SU:STO (I2UM0DW1, (I2UM0MD1, I2UM0DW0 bits) I2UM0MD0 bits) 160 φ...
  • Page 491 Chapter 13 I C Master...

  • Page 492: I2C Master

    13. I C Bus Master 13.1 General Description ML62Q1000 series has two channels of I C bus master that support only the master function on the I C bus specification. The slave function and the low-speed clock (LSCLK) operation are removed from the I...

  • Page 493: Configuration

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.1.2 Configuration Figure 13-1 shows the configuration diagram of the I C bus master circuit. I2CMn_SCL pin I2MnRD，I2MnSTAT Controller Clock I2CMn_SDA pin Shift register HSCLK Generation Circuit I2CMnINT Controller I2MnSA I2MnTD I2MnCON...

  • Page 494: List Of Pins

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.1.3 List of Pins The I/O pins of the I C bus master are assigned to the shared function of the general ports. For details about the pin assignment and the shared function of genral ports, see Chapter 17 "GPIO."...
  • Page 495 ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.2 Description of Registers 13.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF6E0 Reserved 0x00 0xF6E1 Reserved 0x00 0xF6E2 C master 0 receive register I2M0RD 0x00 0xF6E3 Reserved...
  • Page 496 ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.2.2 I C Master n Receive Register (Master) (I2MnRD: n=0,1) I2MnRD is a read-only special function register (SFR) used to store the received data. The I2MnRD is updated after completion of each reception.

  • Page 497: I2C Master N Slave Address Register (I2Mnsa:n=0,1)

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.2.3 I C Master n Slave Address Register (I2MnSA: n=0,1) I2MnSA is a special function register (SFR) to set the address and transmission/reception mode of the slave device. Address: 0xF6E4(I2M0SA), 0xF6F4(I2M1SA) Access:...

  • Page 498: I2C Master N Transmit Data Register (I2Mntd:n=0,1)

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.2.4 I C Master n Transmit Data Register (I2MnTD:n=0,1) I2MnTD is a special function register (SFR) used to set the transmission data. Address: 0xF6E6(I2M0TD), 0xF6F6(I2M1TD) Access: Access size: 8bit Initial value: 0x00...

  • Page 499: I2C Master N Control Register (I2Mncon:n=0,1)

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.2.5 I C Master n Control Register (I2MnCON:n=0,1) I2UnCON is a special function register (SFR) used to control transmission and reception operations. Address: 0xF6E8(I2M0CON), 0xF6F8(I2M1CON) Access: Access size: 8bit Initial value: 0x00...

  • Page 500: I2C Master N Mode Register (I2Mnmod:n=0,1)

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.2.6 I C Master n Mode Register (I2MnMOD: n=0,1) I2UM0MOD is a special function register (SFR) used to set the operation mode. Address: 0xF6EA(I2M0MODL/I2M0MOD), 0xF6EB(I2M0MODH), 0xF6FA(I2M1MODL/I2M1MOD), 0xF6FB(I2M1MODH) Access: Access size: 8/16bit Initial value:...
  • Page 501 ML62Q1000 Series User's Manual Chapter 13 I2C Master [Note] Ÿ When using the high-speed clock for the I C operation, specify the following I C operating clock frequency depending on the mode and the reference frequency of the PLL oscillation.
  • Page 502 ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.2.7 I C Master n Status Register (I2MnSTR: n=0,1) I2MnSTR is a special function register (SFR) to indicate the state of the I C bus unit in the master mode. Address: 0xF6EC(I2M0STAT/I2M0STR), 0xF6ED(I2M0ISR)
  • Page 503 ML62Q1000 Series User's Manual Chapter 13 I2C Master Bit symbol Description name communication terminates when the clock stretch function is not used (I2MnSYN = "0"). To reset this bit, write "1" to this bit or write "0" to I2MnEN bit.

  • Page 504: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.3 Description of Operation 13.3.1 Master Operation The following flow charts describe each operation procedure of the master. 13.3.1.1 Initial Setting of Communication Operation Initial setting start Confirm I2MnST=0 in the I2MnCON register...
  • Page 505 ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.3.1.3 Restart Condition Communication in progress Start the restart condition (I2MnST=1) Set the I2MnCON register Restart communication I2MnRS=1 Start communication I2MnST=1 Output restart condition waveform to I2CMn_SDA and I2CMn_SCL pins. Restart condition completed...
  • Page 506 ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.3.1.5 Control Register Setting Wait State Control register setting wait state start When entering the control register setting wait state, Generate I C bus master 0 interrupt an interrupt (I2CMnINT) is generated by hardware...
  • Page 507 ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.3.1.7 Data Reception Mode Data receive mode start Value (receive data) input to I2CMn_SDA pin Store each bit of received data is stored in synchronization with rising edge of in shift register (8-bit) one by one...

  • Page 508: Communication Operation Timing

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.3.2 Communication Operation Timing Figures 13-2 to 13-4 show the operation timing and control method for each communication mode. Start Stop Restart condition condition condition Register I2MnSA="xxxxxxx0B" I2MnTD="xxH" I2MnTD="xxH" I2MnTD="xxH" setting I2MnCON="01H"...
  • Page 509 ML62Q1000 Series User's Manual Chapter 13 I2C Master Figure 13-5 shows the operation timing and control method when an acknowledgment error occurs. Acknowledge error Register I2MnSA="xxxxxxx0B" setting I2MnCON="01H" I2MnCON="02H" I2CMn_SDA pin Values of I2MnSA I2MnINT I2MnST bit I2MnRD register Values of I2MnSA...

  • Page 510: Operation Waveforms

    ML62Q1000 Series User's Manual Chapter 13 I2C Master 13.3.3 Operation Waveforms Figure 13-7 shows the operation waveforms of the I2CMn_SDA and I2CMn_SCL pins and the I2MnBB flag. Tables 13-4 and 13-5 show the relationship between communication speeds and HSCLK clock counts.
  • Page 511 ML62Q1000 Series User's Manual Chapter 13 I2C Master Table 13-5 Relationship between Communication Speeds and HSCLK Clock Counts (at HSCLK=16MHz) I2MnMOD register Communication Speed reduction speed HD:STA HD:DAT HIGH SU:STA SU:DAT SU:STO (I2MnDW1 and (I2MnMD1 and I2MnDW0 bits) I2MnMD0 bits) 160 φ...
  • Page 512 Chapter 14 DMA Controller...

  • Page 513: Dma Controller

    14. DMA Controller 14.1 General Description ML62Q1000 series has two channels of the DMA (Direct Memory Access) Controller, which enables to transfer data between a peripheral circuit (SFR) and the built-in RAM without the CPU operation. Table 14-1 in the section 14.3.5 "DMA Transfer Target Block" shows available peripheral bocks to use as the DMA transfer source or destination.

  • Page 514: Features

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.1.1 Features · Transfer unit: 8bit/16bit · Transfer count: 1 to 1024 time · Transfer cycle: 2 cycle (CPU operation has priority if the access is competed) · Transfer address: Fixed address / Increment address / Decrement address ·...

  • Page 515: Configuration

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.1.2 Configuration Figure 14-2 shows the configuration of the DMA Control circuit. A/D converter DMA request Transfer Serial communication request DMA request Register 16bit timer DMA request Channel priority control DCnMODL Functional timer DMA request...

  • Page 516: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.2 Description of Registers 14.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF700 DC0MODL 8/16 0x00 DMA channel 0 transfer mode register DC0MOD 0xF701 DC0MODH 0x00 0xF702 DC0TNL...

  • Page 517: Dma Channel N Transfer Mode Register (Dcnmod: N = 0, 1)

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.2.2 DMA Channel n Transfer Mode Register (DCnMOD: n = 0, 1) DCnMOD is a special function register (SFR) used to set the transfer trigger, transfer unit and addressing mode of the transfer source and transfer destination.
  • Page 518 ML62Q1000 Series User's Manual Chapter 14 DMA Controller 11011: External 3 DMA request 11100: External 4 DMA request 11101: External 5 DMA request 11110: External 6 DMA request 11111: External 7 DMA request 7 to 5 Reserved DCnDS This bit is used to set the transfer data unit of channel n.

  • Page 519: Dma Channel N Transfer Count Register (Dcntn: N = 0, 1)

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.2.3 DMA Channel n Transfer Count Register (DCnTN: n = 0, 1) DCnTN is a special function register (SFR) used to set the transfer count for channel n. Address: 0xF702(DC0TNL/DC0TN), 0xF703(DC0TNH), 0xF70A(DC1TNL/DC1TN), 0xF70B(DC1TNH)

  • Page 520: Dma Channel N Transfer Source Address Register (Dcnsa: N = 0, 1)

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.2.4 DMA Channel n Transfer Source Address Register (DCnSA: n = 0, 1) DCnSA is a special function register (SFR) used to set the transfer source address of channel n. Specify an existing SFR address or RAM address. If a non-existing address is set, operation is not guaranteed.

  • Page 521: Dma Channel N Transfer Destination Address Register (Dcnda: N = 0, 1)

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.2.5 DMA Channel n Transfer Destination Address Register (DCnDA: n = 0, 1) DCnSA is a special function register (SFR) used to set the transfer destination address of channel n. Specify an existing SFR address or RAM address. If a non-existing address is set, operation is not guaranteed.

  • Page 522: Dma Transfer Enable Register (Dcen)

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.2.6 DMA Transfer Enable Register (DCEN) DCEN is a special function register (SFR) used to enable the DMA transfer and set the behaivor in the case two channels competed to work. Address:...

  • Page 523: Dma Status Register (Dstat)

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.2.7 DMA Status Register (DSTAT) DSTAT is a special function register (SFR) used to indicate the status of the DMA transfer channels. Address: 0xF722(DCSTATL/DSTAT), 0xF723(DCSTATH) Access: Access size: 8/16bit Initial value: 0x0000...

  • Page 524: Dma Interrupt Status Clear Register (Diclr)

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.2.8 DMA Interrupt Status Clear Register (DICLR) DICLR is a special function register (SFR) used to clear the interrupt status of the DMA transfer channel. Address: 0xF724 Access: Access size: 8bit Initial value:...

  • Page 525: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.3 Description of Operation The DMA controller can be used to transfer data between SFRs (special function registers) of peripheral circuits and data memory (RAM) without involving the CPU. After selecting the transfer unit, transfer count, transfer addressing, and transfer trigger followed by enabling the DMA transfer, once the specified transfer count is completed, the DMA controller interrupt request is generated.
  • Page 526 ML62Q1000 Series User's Manual Chapter 14 DMA Controller The following chart shows the DMA controller termination procedure. Start n=0 or 1 Confirm operation termination with the DCnISTA bit of the DSTAT Confirm transfer register status Write "1" to the DICLRn bit of the DICLR register...

  • Page 527: Dma Transfer Operation Timing Diagram

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.3.2 DMA transfer Operation Timing Diagram The following chart shows an operation timing diagram with the transfer source set to RAM/increment addressing, transfer destination to SFR/fixed address, transfer unit to 8-bit, and transfer count to twice.

  • Page 528: Uart Continuous Transmission Using Dma Transfer

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.3.3 UART Continuous Transmission Using DMA Transfer The following flow chart describes an example of UART continuous transmission using DMA transfer. See Chapter 11 "Serial Communication Unit" for details of UART. [Operation specifications] ・...

  • Page 529: Uart Continuous Reception Using Dma Transfer

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.3.4 UART Continuous Reception Using DMA Transfer The following flow chart describes an example of UART continuous reception using DMA transfer. See Chapter 11 "Serial Communication Unit" for details of UART. [Operation specifications] ・...

  • Page 530: Dma Transfer Target Block

    ML62Q1000 Series User's Manual Chapter 14 DMA Controller 14.3.5 DMA Transfer Target Block The following table shows function blocks available for the DMA transfer source/destination. Table 14-1 DMA Transfer Target Block Function block Memory Transfer ● ● ● ● ●...

  • Page 531: Buzzer

    Chapter 15 Buzzer...

  • Page 532: General Description

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15. Buzzer 15.1 General Description The buzzer circuit generates a base signal in combination of 8 frequencies and 15 duties and outputs the signal in four modes. Intermittent sound 1 mode: Arbitrary period...

  • Page 533: Features

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.1.1 Features · Four buzzer modes (Intermittent sound 1, Intermittent sound 2, Single sound and Continuous sound) · Eight frequencies (4.096 kHz to 293 Hz) · 15 duties (1/16 to 15/16 = 6.25% to 93.75%) Only seven duties (1/8 to 7/8) are available when the buzzer frequency is 4.096 kHz.

  • Page 534: Configuration

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.1.2 Configuration Figure 15-2 shows the configuration of the buzzer circuit. T8HZ T1HZ LSCLK BZ0P pin Duty Buzzer output Buzzer frequency generation mode choice BZ0N pin generation circuit circuit circuit Control circuit Frequency choise...
  • Page 535 ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.1.3 List of Pins The output pins of the buzzer signal are assigned to the shared function of the general port. Pin name Function BZ0P Buzzer 0 positive phase output BZ0N Buzzer 0 negative phase output Table 15-1 shows the list of the general ports used for the buzzer output and the register settings of the ports.

  • Page 536: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.2 Description of Registers 15.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF0C0 Buzzer 0 control register BZ0CON 0x00 0xF0C1 Reserved 0x00 0xF0C2 BZ0MODL 8/16 0x00 Buzzer 0 mode register...

  • Page 537: Buzzer 0 Control Register (Bz0Con)

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.2.2 Buzzer 0 Control Register (BZ0CON) BZ0CON is a special function register (SFR) used to control the buzzer. ： Address 0xF0C0 (BZ0CON) ： Access ： Access size 8bit ： Initial value 0x00 Word...

  • Page 538: Buzzer 0 Mode Register (Bz0Mod)

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.2.3 Buzzer 0 Mode Register (BZ0MOD) BZ0MOD is a special function register (SFR) used to set the buzzer output waveform. Address: 0xF0C2 (BZ0MOD/ BZ0MODL), 0xF0C3(BZ0MODH) Access: Access size: 8/16bit Initial value: 0x0000 Word...
  • Page 539 ML62Q1000 Series User's Manual Chapter 15 Buzzer Bit symbol Description name 1, 0 BZ0MD1， These bits are used to choose the buzzer output mode. BZ0MD0 Intermittent sound 1 output mode (initial value) Sound like: "Beep Beep Beep Beep Beep Beep Beep Beep"...

  • Page 540: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.3 Description of Operation 15.3.1 Intermittent Sound 1 Mode 15.3.1.1 Operation of Intermittent Sound 1 Mode Figure 15-3 shows the buzzer output waveform of the intermittent sound 1 mode. Each of black areas indicates a period of time during which the buzzer signal pulse is output.
  • Page 541 ML62Q1000 Series User's Manual Chapter 15 Buzzer [Note] Ÿ The buzzer output may be started in the middle of the buzzer waveform depending on timing the BZ0RUN bit of the BZ0CON register is set to "1". If it causes a problem, take one of the following...

  • Page 542: Intermittent Sound 2 Mode

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.3.2 Intermittent Sound 2 Mode 15.3.2.1 Operation of Intermittent Sound 2 Mode Figure 15-5 shows the buzzer output waveform of the intermittent sound 2 mode. Each of black areas indicates a period of time during which the buzzer signal pulse is output.

  • Page 543: Single Sound Mode

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.3.3 Single Sound Mode 15.3.3.1 Single Sound Mode Operation Figure 15-7 shows the buzzer output waveform of the single sound mode. Each of black areas indicates a period of time during which the buzzer signal pulse is output.

  • Page 544: Continuous Sound Mode

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.3.4 Continuous Sound Mode 15.3.4.1 Continuous Sound Mode Operation Figure 15-9 shows the buzzer output waveform of the continuous sound mode. Each of black areas indicates a period of time during which the buzzer signal pulse is output.

  • Page 545: Common Operation

    ML62Q1000 Series User's Manual Chapter 15 Buzzer 15.3.5 Common Operation 15.3.5.1 Buzzer Output Start and Stop Timing Figures 15-11 to 15-15 show buzzer signal output start and stop timing waveforms. BZ0RUN LSCLK (32.768 kHz) BZ0P pin BZ0N pin 4.096kHz (1) When positive logic is applied (BZ0INI bit of BZ0MOD register=0) Setting example: buzzer frequency=4.096 kHz, duty=3/8 (37.5%)
  • Page 546 ML62Q1000 Series User's Manual Chapter 15 Buzzer BZ0RUN LSCLK (32.768 kHz) BZ0P pin BZ0N pin 4.096kHz (1) When positive logic is applied (BZ0INI bit of BZ0MOD register=0) Setting example: buzzer frequency=4.096 kHz, duty=3/8 (37.5%) BZ0RUN LSCLK (32.768 kHz) BZ0P pin BZ0N pin 4.096kHz...
  • Page 547 ML62Q1000 Series User's Manual Chapter 15 Buzzer BZ0RUN LSCLK (32.768 kHz) BZ0P pin BZ0N pin 4.096kHz 4.096kHz (1) When positive logic is applied (BZ0INI bit of BZ0MOD register=0) Setting example: buzzer frequency=4.096 kHz, duty=3/8 (37.5%) BZ0RUN LSCLK (32.768 kHz) BZ0P pin BZ0N pin 4.096kHz...
  • Page 548 ML62Q1000 Series User's Manual Chapter 15 Buzzer T8HZ bit T1HZ and T8HZ LSCLK (32.768 kHz) BZ0P pin BZ0N pin 4.096kHz (1) When positive logic is applied (BZ0INI bit of BZ0MOD register=0) Setting example: buzzer frequency=4.096 kHz, duty=3/8 (37.5%) T8HZ bit...
  • Page 549 ML62Q1000 Series User's Manual Chapter 15 Buzzer T8HZ bit T1HZ and T8HZ LSCLK (32.768 kHz) BZ0P pin BZ0N pin 4.096kHz (1) When positive logic is applied (BZ0INI bit of BZ0MOD register=0) Setting example: buzzer frequency=4.096 kHz, duty=3/8 (37.5%) T8HZ bit...

  • Page 550: Simplified Rtc

    Chapter 16 Simplified RTC...

  • Page 551: General Description

    16.1 General Description ML62Q1000 series has the simplified RTC (RTC: Real Time Clock). The simplified RTC counts up from 00 minutes 00 seconds to 59 minutes 59 seconds in the unit of one second and also generates an interrupt request periodically.

  • Page 552: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 16 Simplified RTC 16.2 Description of Registers 16.2.1 List of Registers Symbol name Initial Address Name Size value Byte Word 0xF0C8 Simplified RTC acceptor SRTCACP 0x00 0xF0C9 Reserved register 0x00 0xF0CA SRTCSEC 8/16 0x00 Simplified RTC minute/second counter...

  • Page 553: Simplified Rtc Acceptor (Srtcacp)

    ML62Q1000 Series User's Manual Chapter 16 Simplified RTC 16.2.2 Simplified RTC Acceptor (SRTCACP) This register is a write-only special function register (SFR) used to enable writing to the simplified RTC minute/second register (SRTCMAS). "0x00" is read for reading the SRTCACP register.

  • Page 554: Simplified Rtc Minute/Second Counter (Srtcmas)

    ML62Q1000 Series User's Manual Chapter 16 Simplified RTC 16.2.3 Simplified RTC Minute/Second Counter (SRTCMAS) This register is a special function register (SFR) used to show the minute/second data. After enabling to write to the SRTCMAS register using the SRTCACP register, data can be written to the SRTCMAS register.
  • Page 555 ML62Q1000 Series User's Manual Chapter 16 Simplified RTC [Note] Ÿ When reading the SRTCMAS register, read it twice and check that the two values coincide with each other to prevent reading of undefined data during counting up. Ÿ If the data outside the range from 00 minutes 00 seconds to 59 minutes 59 seconds is written to the SRTCMAS register, the register will be set to the initial value.

  • Page 556: Simplified Rtc Control Register (Srtccon)

    ML62Q1000 Series User's Manual Chapter 16 Simplified RTC 16.2.4 Simplified RTC Control Register (SRTCCON) This register is a special function register (SFR) used to set a periodical interrupt request. Address: 0xF0CC (SRTCCON) Access: Access size: 8 bit Initial value: 0x00...

  • Page 557: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 16 Simplified RTC 16.3 Description of Operation The simplified RTC starts operation after a power-on reset is released. Since the value of the PORSTAT bit of the SRTCMAS register is "1" after the power-on reset is released, data needs to be written to the SRTCMAS register to set the minute and second.

  • Page 558: Simplified Rtc Setting Example For Writing Time Data

    ML62Q1000 Series User's Manual Chapter 16 Simplified RTC 16.3.2 Simplified RTC Setting Example for Writing Time Data Figure 16-3 shows an example of setting the simplified RTC to write 29 minutes 39 seconds to the SRTCMAS register. Setting start Set to disable periodical interrupt request SRTCCON setting SRTCCON = 0x00 ;...
  • Page 559 Chapter 17 GPIO...

  • Page 560: General Purpose Port

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17. General Purpose Port 17.1 General Description The general pupose port is used as an input port or an output mode. One general input/output port is configured with the max. eight pins and the input and output is switchable on each pin.

  • Page 561: Features

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.1.1 Features · Input or output can be chosen in each pin · Pull-up resister can be chosen in each pin · CMOS output or N-channel open drain output is can be chosen in each pin ·...

  • Page 562: Configuration

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.1.2 Configuration Figure 17-1 shows the configuration of the general purpose port. Pull-up Data bus Controller PnMOD01 PnMOD23 PnMOD45 PnMOD67 PnPMD PnPSL PnDI, PnDO Output Pn0 to Pn7 Controller Output in a shared function...

  • Page 563: List Of Pins

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.1.3 List of Pins Table 17-1 List of Pins Available / Unavailable ML62Q1300 group ML62Q1500 / ML62Q1700 group Primary Name Function ● ● ● ● ● Crystal resonator − − −...
  • Page 564 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Available / Unavailable ML62Q1300 group ML62Q1500 / ML62Q1700 group Primary Name Function ● ● ● I/O port ● ● ● ● I/O port ● ● ● I/O port ● ● ●...
  • Page 565 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Available / Unavailable ML62Q1300 group ML62Q1500 / ML62Q1700 group Primary Name Function ● I/O port ● I/O port ● I/O port ● I/O port ● I/O port ● I/O port ●...

  • Page 566: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2 Description of Registers 17.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF200 P0DI 8/16 0xFF Port 0 data register 0xF201 P0DO 0x00 0xF202 P0MOD0 8/16 0x05...
  • Page 567 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Symbol Initial Address Name Size Value Byte Word 0xF22A P2PMDL 8/16 0x00 Port 2 pulse mode register P2PMD 0xF22B P2PMDH 0x00 0xF22C P2PSLL 8/16 0x00 Port 2 pulse selection register P2PSL...
  • Page 568 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Symbol Initial Address Name Size Value Byte Word 0xF260 P6DI 8/16 0xFF Port 6 data register 0xF261 P6DO 0x00 0xF262 P6MOD0 8/16 0x00 Port 6 mode register 01 P6MOD01 0xF263 P6MOD1...
  • Page 569 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Symbol Initial Address Name Size Value Byte Word 0xF298 P9MOD6 8/16 0x00 Port 9 mode register 67 P9MOD67 0xF299 P9MOD7 0x00 0xF29A Reserved 0x00 0xF29F 0xF2A0 PADI 8/16 0xFF Port A data register...
  • Page 570 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Table 17-2 List of Registers / Bits Available / Unavailable * ML62Q1500 Control register / bit * ML62Q1300 ML62Q1700 group group Port Name Name ● ● ● ● ● PI00 PXT0DI...
  • Page 571 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Available / Unavailable * ML62Q1500 Control register / bit * ML62Q1300 ML62Q1700 group group Port Name Name ● ● ● P40DO P40DI P4MOD0 ● ● ● ● P41DO P41DI P4MOD1 ●...
  • Page 572 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Available / Unavailable * ML62Q1500 Control register / bit * ML62Q1300 ML62Q1700 group group Port Name Name ● ● P80DO P80DI P8MOD0 ● ● P81DO P81DI P8MOD1 ● ● P82DO P82DI P8MOD2 ●...

  • Page 573: Port N Data Register (Pnd:n=0 To 9, A, B)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.2 Port n Data Register (PnD:n＝0 to 9, A, B) PnD is a special function register (SFR) used to read the level of the port n pin and write output data.

  • Page 574: Port N Mode Register 01 (Pnmod01:N=0 To 9, A, B)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.3 Port n Mode Register 01 (PnMOD01:n＝0 to 9, A, B) PnMOD01 is a special function register (SFR) to choose the input/output mode, input/output status, and shared function of Pn0 pin and Pn1 pin.
  • Page 575 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Bit symbol Description name Pn1PU This bit is used to enable the internal pull-up resistor of Pn1 pin. The internal pull-up resistor can be enabled on following conditions of the port.
  • Page 576 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Bit symbol Description name Pn0IE This bit is used to enable the input of Pn0 pin Disable the input (initial value) Enable the input [Note] Ÿ Be sure to set the PnMODm(n＝0 to B, m=0 to 7) registers before setting EICON0, EIMOD0 and IE1 registers.

  • Page 577: Port N Mode Register 23 (Pnmod23:N=0 To 9, A, B)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.4 Port n Mode Register 23 (PnMOD23:n＝0 to 9, A, B) PnMOD23 is a special function register (SFR) to choose the input/output mode, input/output status, and shared function of Pn2 pin and Pn3 pin.
  • Page 578 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Bit symbol Description name Pn3PU This bit is used to enable the internal pull-up resistor of Pn3 pin. The internal pull-up resistor can be enabled on following conditions of the port.
  • Page 579 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Bit symbol Description name Pn2IE This bit is used to enable the input of Pn2 pin Disable the input (initial value) Enable the input [Note] Ÿ Be sure to set the PnMODm(n＝0 to B, m=0 to 7) registers before setting EICON0, EIMOD0 and IE1 registers.

  • Page 580: Port N Mode Register 45 (Pnmod45:N=0 To 2, 4 To 9, A, B)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.5 Port n Mode Register 45 (PnMOD45:n＝0 to 2, 4 to 9, A, B) PnMOD45 is a special function register (SFR) to choose the input/output mode, input/output status, and shared function of Pn4 pin and Pn5 pin.
  • Page 581 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Bit symbol Description name Pn5PU This bit is used to enable the internal pull-up resistor of Pn5 pin. The internal pull-up resistor can be enabled on following conditions of the port.
  • Page 582 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Bit symbol Description name Pn4IE This bit is used to enable the input of Pn4 pin Disable the input (initial value) Enable the input [Note] Ÿ Be sure to set the PnMODm(n＝0 to B, m=0 to 7) registers before setting EICON0, EIMOD0 and IE1 registers.

  • Page 583: Port N Mode Register 67 (Pnmod67:N=0 To 2, 4 To 9, A, B)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.6 Port n Mode Register 67 (PnMOD67:n＝0 to 2, 4 to 9, A, B) PnMOD67 is a special function register (SFR) to choose the input/output mode, input/output status, and shared function of Pn6 pin and Pn7 pin.
  • Page 584 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Bit symbol Description name Pn7PU This bit is used to enable the internal pull-up resistor of Pn7 pin. The internal pull-up resistor can be enabled on following conditions of the port.
  • Page 585 ML62Q1000 Series User's Manual Chapter 17 General Purpose Port Bit symbol Description name Pn6IE This bit is used to enable the input of Pn6 pin Disable the input (initial value) Enable the input [Note] Ÿ Be sure to set the PnMODm(n＝0 to B, m=0 to 7) registers before setting EICON0, EIMOD0 and IE1 registers.

  • Page 586: Port N Pulse Mode Register (Pnpmd:n=0 To 3)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.7 Port n Pulse Mode Register (PnPMD:n＝0 to 3) PnPMD is a special function register (SFR) used when outputing a carrier frequency (pulse output) to the port n. See Table 17-2 "List of Registers / Bits" to check avaible pins and bits.

  • Page 587: Port N Pulse Selection Register (Pnpsl:n=0 To 3)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.8 Port n Pulse Selection Register (PnPSL:n＝0 to 3) PnPSL is a special function register (SFR) used to choose the timer for generating the carrier frequency to the port n. See Table 17-2 "List of Registers / Bits" to check avaible pins and bits.

  • Page 588: Portxt Data Input Register (Pxtdi)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.9 PORTXT data input register (PXTDI) PXTDI is a special function register (SFR) used for reading the level of XT0/XT1 pin. The level of XT0/PI00 and XT1/PI01 is readable in the input mode.

  • Page 589: Portxt Mode Register 01 (Pxtmod01)

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.2.10 PORTXT mode register 01 (PXTMOD01) PXTMOD01 is a special function register (SFR) used to choose the input mode of the XT0/PI00 pin and XT1/PI01 pin. The port is unavailable to use when connecting the crystal resonator.

  • Page 590: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.3 Description of Operation 17.3.1 Input Each pin of port n sets the PnmIE bit of the PnMODm register to enter the state where input is enabled. In the state with input enabled, the pin level can be read using the PnDI register.

  • Page 591: Carrier Frequency Output

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.3.5 Carrier Frequency Output 17.3.5.1 Carrier Frequency Output Operation A carrier frequency signal can be output from port n by setting the PnPMD Register. The carrier frequency output can be applied to all output except analogue output.

  • Page 592: Port Output Level Test

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.3.6 Port Output Level Test The level specified in the PnDO register can be read from the PnDI register by setting the PnmOE bit of the PnMODm register to "1" and the PnmIE bit to "1".

  • Page 593: Notes For Using The P00/Test0 Pin

    ML62Q1000 Series User's Manual Chapter 17 General Purpose Port 17.3.8 Notes for using the P00/TEST0 pin P00/TEST0 pin is used for the general port, the on-chip debug function or ISP funcction. Confirm following notes in each usage. 17.3.8.1 When using as the general purpose port Make sure following notes when using the reset function by the RESET_N pin.

  • Page 594: External Interrupt Function

    Chapter 18 External Interrupt Function...

  • Page 595: General Description

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18. External Interrupt Function 18.1 General Description The external interrupt function generates interrupts by signals input to the general ports. The interrupt channel has each dedicated interrupt vector. For details of the interrupt vector, see Chapter 5 "Interrupt".

  • Page 596: Features

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.1.1 Features · Maskable nine interrupts (one vector is shared for four external input pins: Expanded external interrupt) · Available to choose the interrupt mode: interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode or both-edge interrupt mode ·...

  • Page 597: Configuration

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.1.2 Configuration Figure 18-1 shows the configuration of the external interrupt function (EXI0 to EXI7) EXI0INT/EXI0 DMA request P02/EXI0 EXI1INT/EXI1 DMA request P03/EXI1 EXI2INT/EXI2 DMA request P04/EXI2 Sampling Interrupt EXI3INT/EXI3 DMA request...
  • Page 598 ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.1.3 List of Pins The external interrupt is assigned to the primary function of the general port. For details of pin assignment, see Chapter 17 "GPIO". Pin name Function EXI0 External Interrupt Input 0...
  • Page 599 ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.2 Description of Registers 18.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF044 EICON0L 8/16 0x00 External Interrupt Control register 0 EICON0 0xF045 EICON0H 0x00 0xF046 Reserved...
  • Page 600 ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.2.2 External Interrupt Control Register 0 (EICON0) EICON0 is a special function register (SFR) used to choose the detection edeg of the external interrupt input (EXI0 to EXI7). Detecting the edege can generate the external interrupt (EXI0INT to EXI7INT).

  • Page 601: External Interrupt Mode Register 0 (Eimod0)

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.2.3 External Interrupt Mode Register 0 (EIMOD0) EIMOD0 is a special function register (SFR) to choose the sampling clock and with/without sampling for the external interrupt (EXI0 to EXI7). Only one sampling clock can be chosen and it is shared for all the interrupt EXI0 to EXI7.
  • Page 602 ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function [Note] (*1) Ÿ In the STOP/STOP-D/HALT-H mode, no sampling is performed regardless of the values set in PI7SM to PI0SM bits of EIMOD0 register since the sampling clock stops. When choosing "with sampling" and...

  • Page 603: Expanded External Interrupt Control Register 0 (Eeicon0)

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.2.4 Expanded External Interrupt Control Register 0 (EEICON0) EEICON0 is a special function register (SFR) to choose the detection edge of EXI8 to EXI11. Address： 0xF0E4(EEICON0L/EEICON0), 0xF0E5(EEICON0H) Access： Access size： 8/16bit Initial value：...

  • Page 604: Expanded External Interrupt Mode Register 0 (Eeimod0)

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.2.5 Expanded External Interrupt Mode Register 0 (EEIMOD0) EEIMOD0 is a special function register (SFR) to choose the sampling clock and with/without sampling for the external interrupt (EXI8 to EXI11). Address：...

  • Page 605: Expanded External Interrupt Mode Register 1(Eeimod1)

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.2.6 Expanded External Interrupt Mode Register 1(EEIMOD1) EEIMOD1 is a special function register (SFR) to choose dividing ratio of the sampling clock for the external interrupt (EXI8 to EXI11). Address： 0xF0EA(EEIMOD1L/EEIMOD1), 0xF0EB(EEIMOD1H) Access：...

  • Page 606: Expanded External Interrupt Status Register (Eeistat)

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.2.7 Expanded External Interrupt Status Register (EEISTAT) EEISTAT is a special function register (SFR) used to indicate the expanded external interrupt status. The EEI3S bit to EEI0S bit is reset to "0" by writing "1" to the same number of bit in the EEINTC register.

  • Page 607: Expanded External Interrupt Clear Register (Eeintc)

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.2.8 Expanded External Interrupt Clear Register (EEINTC) EEINTC is a special function register (SFR) used to clear the expanded external interrupt status. The EEI3C bit to EEI0C bit is set to "1", the interrupt request indicated by the same number of bit in the EEISTAT register gets cleared.

  • Page 608: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.3 Description of Operation 18.3.1 Interrupt Request Timing Figure 18-3 shows the interrupt generation timing without sampling (when the rising-edge/falling-edge/both-edge interrupt mode is chosen). Figure 18-4 shows the interrupt generation timing with sampling (when the rising-edge interrupt mode is chosen).

  • Page 609: External Trigger Signal

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function Sampling clock System clock EXI0 to EXI11 Coincidence determined three times EXI0INT to EXI11INT Interrupt request Figure 18-4 External Interrupt Generation Timing (with Sampling, with Rising-edge Interrupt Mode Chosen) 18.3.2 External Trigger Signal Pins assigned with external interrupt can be used as external trigger signals (EXTRG0 to EXTRG7) for the 16-bit timer and function timer.

  • Page 610: External Interrupt Setting Flow

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.3.3 External Interrupt Setting Flow Figure 18-6 shows the external interrupt setting flow. Setting start Required if using HSCLK for the sampling clock. Set High-speed clock. Set ports to the input mode in PnMODxx registers.

  • Page 611: Expanded External Interrupt Setting Flow

    ML62Q1000 Series User's Manual Chapter 18 External Interrupt Function 18.3.4 Expanded External Interrupt Setting Flow Figure 18-7 shows the expanded external interrupt setting flow. Setting Start Set ports to the input mode in PnMODxx registers. Set port mode (xx=01, 23, 45, 67)

  • Page 612: Crc (Cycle Redundancy Check) Generator

    Chapter 19 CRC Generator...

  • Page 613: General Description

    19. CRC Generator 19.1 General Description ML62Q1000 series has the CRC (Cycle Redundancy Check) generator that performs CRC calculation and generates the CRC data used for error detection in serial communications. Also, the CRC generator has automatic CRC calculation mode to check data in program memory, available in HALT mode or HALT-H mode.

  • Page 614: Features

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.1.1 Features · Manual CRC generation mode Generates CRC data from data set in CRC calculation register by the software Calculation unit is 8bit · Automatic CRC generation mode Automatic CRC calculation by the hardware to check data in program memory in HALT or HALT-H mode and...

  • Page 615: Configuration

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.1.2 Configuration Figure 19-2 shows the configuration of the CRC generator. Automatic CRC generation completion interrupt request HALT/HALT-H mode Match Arithmetic Comparator Arithmetic circuit Program Control Memory CRCSSEG CRCESEG CRCMOD CRCDATA CRCRES...
  • Page 616 ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.2 Description of Registers 19.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF0D0 CRCSADL 8/16 0x00 Automatic CRC Calculation Start Address CRCSAD Setting Register 0xF0D1 CRCSADH 0x00 0xF0D2...

  • Page 617: Automatic Crc Calculation Start Address Setting Register (Crcsad)

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.2.2 Automatic CRC Calculation Start Address Setting Register (CRCSAD) CRCSAD is a special function register (SFR) used to set the start address of automatic CRC calculation. The address of the program code area set in this register is incremented during the automatic CRC calculation mode.

  • Page 618: Automatic Crc Calculation End Address Setting Register (Crcead)

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.2.3 Automatic CRC Calculation End Address Setting Register (CRCEAD) CRCEAD is a special function register (SFR) used to set the end address of automatic CRC calculation. Address: 0xF0D2 Access: Access size: 8/16bit...

  • Page 619: Automatic Crc Calculation Start Segment Setting Register (Crcsseg)

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.2.4 Automatic CRC Calculation Start Segment Setting Register (CRCSSEG) CRCSSEG is a special function register (SFR) used to set the start segment of automatic CRC calculation. The address of the program code area set in this register is incremented during the automatic CRC calculation mode.

  • Page 620: Automatic Crc Calculation End Segment Setting Register (Crceseg)

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.2.5 Automatic CRC Calculation End Segment Setting Register (CRCESEG) CRCESEG is a special function register (SFR) used to set the end segment of automatic CRC calculation. Address: 0xF0D6 Access: Access size: 8bit...

  • Page 621: Crc Data Register (Crcdata)

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.2.6 CRC Data Register (CRCDATA) CRCDATA is a special function register (SFR) used to set the CRC calculation data. Set it by eight bits. One clock after writing data to the CRCDATA, the calculation result is stored in the CRC Calculation Result Register (CRCRES).

  • Page 622: Crc Calculation Result Register (Crcres)

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.2.7 CRC Calculation Result Register (CRCRES) CRCRES is a special function register (SFR). The CRC calculation result is stored by the hardware. Set data to the CRCRES as an initial data for the CRC calculation.

  • Page 623: Automatic Crc Mode Register (Crcmod)

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.2.8 Automatic CRC Mode Register (CRCMOD) CRCMOD is a special function register (SFR) used to control the automatic CRC calculation mode. Address: 0xF0DC Access: Access size: 8bit Initial value: 0x00 Word Byte...

  • Page 624: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.3 Description of Operation Two modes are available for the CRC calculator: manual CRC calculation mode and automatic CRC calculation mode. · Manual CRC Calculation Mode CRC calculation is executed by hardware as needed through writing data to the CRC calculation register using software.
  • Page 625 ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.3.1.1 Example of Use of Manual CRC Calculation Mode The following chart shows the process flow of serial transmission with the CRC calculation result attached to data. In this example, 11-byte data with 0x21 in the beginning is used as transmit data, and calculation result is obtained using the calculation shift direction in LSB first mode.
  • Page 626 ML62Q1000 Series User's Manual Chapter 19 CRC Generator The following chart shows the CRC calculation process flow with the CRC calculation result attached to the serial receive data. In this example, 13-byte data with 0x21 in the beginning is used as calculation data. From the calculation data, calculation result is obtained using the calculation shift direction in LSB first mode.
  • Page 627 ML62Q1000 Series User's Manual Chapter 19 CRC Generator The following chart shows the process flow of serial transmission with the CRC calculation result attached to data. In this example, 11-byte data with 0x21 in the beginning is used as transmit data, and calculation result is obtained using the calculation shift direction in MSB first mode.
  • Page 628 ML62Q1000 Series User's Manual Chapter 19 CRC Generator The following chart shows the CRC calculation process flow with the CRC calculation result attached to the serial receive data. In this example, 13-byte data with 0x21 in the beginning is used as calculation data. From the calculation data, calculation result is obtained using the calculation shift direction in MSB first mode.
  • Page 629 ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.3.1.2 Operation Timing Chart in Manual CRC Calculation Mode Set the initial value of CRC calculation in the CRCRES register. If 8-bit data is written to the CRCDATA register, the calculation result is stored in the CRCRES register on the next clock rising-edge. The CRC calculation result can be checked anytime by reading the CRCRES register.

  • Page 630: Automatic Crc Calculation Mode

    ML62Q1000 Series User's Manual Chapter 19 CRC Generator 19.3.2 Automatic CRC Calculation Mode In the automatic CRC calculation mode, an arbitrary program memory area is automatically CRC-calculated in the HALT/HALT-H mode and the result is output to the CRC calculation result register (CRCRES).
  • Page 631 (MCINTEL). See Chapter 29 "Safety Function" for details of the MCINTEL register. See "ML62Q1000 Series Self-test Sample Software AP Notes" and "HTU8 User's Manual" for details of self-test program using the automatic CRC calculation mode or how to generate expected values.
  • Page 632 Chapter 20 Analog Comparator...

  • Page 633: Analog Comparator

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator 20. Analog Comparator 20.1 General Description The Analog Comparator enables to use following functions. ž Compare voltages input to the two pins ž Compare a voltage input to the one pin with the internal reference voltage (Approx. 0.8V) Table 20-1 shows the number of channels.

  • Page 634: Features

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator 20.1.1 Features · The voltage input to the two pins are comparable or the voltage input to the one pin are comparable with the internal reference voltage (approx. 0.8V). · There types of interrupt timing generated by the voltage comparison are available.

  • Page 635: Configuration

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator 20.1.2 Configuration Figure 20-1 shows the configuration of the analog comparator. CMPnD CMPnP pin Interrupt Sampling CMPnINT Latch CMPnM pin Control Control CMPnVREF Frequency 0.8V HSCLK CMPnMOD CMPnCON division Reference LSCLK circuit...

  • Page 636: List Of Pins

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator 20.1.3 List of Pins The I/O pins of the Analog Comparator are assigned to the shared function of the general ports. For details of pin assignment, see Chapter 17 "GPIO". Pin name...

  • Page 637: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator 20.2 Description of Registers 20.2.1 List of Registers Symbol Initial Address Name Size value Byte Word 0xF840 CMP0CON Comparator 0 control register 0x00 0xF841 Reserved 0x00 0xF842 CMP0MODL 8/16 0x00 Comparator 0 mode register...

  • Page 638: Comparator N Control Register (Cmpncon: N=0,1)

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator 20.2.2 Comparator n Control Register (CMPnCON: n=0,1) CMPnCON is a special function register (SFR) used to control the analog comparator. Address： 0xF840(CMP0CON)，0xF848(CMP1CON) Access： Access size： 8bit Initial value： 0x00 Word Byte CMPnCON...

  • Page 639: Comparator N Mode Register (Cmpnmod: N=0,1)

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator 20.2.3 Comparator n Mode Register (CMPnMOD: n=0,1) CMPnMOD is a special function register (SFR) used to set the operation mode of the analog comparator. Address: 0xF842(CMP0MODL/CMP0MOD), 0xF843(CMP0MODH), 0xF84A(CMP1MODL/CMP1MOD), 0xF84B(CMP1MODH), Access: Access size:...
  • Page 640 ML62Q1000 Series User's Manual Chapter 20 Analog Comparator [Note] (*1) Ÿ In the STOP/STOP-D/HALT-H mode, no sampling is performed regardless of the values set in CMPnCS1 bit and CMPnCS0 bit since the sampling clock stops. When choosing "with sampling" and...

  • Page 641: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator 20.3 Description of Operation 20.3.1 Analog Comparator Operation Figure 20-2 shows an analog comparator operation overview. Start CMPnEN="1" Enable analog Start comparison between the CMPnP pin input voltage and CMPnM comparator operation pin input voltage, or between CMPnP pin input voltage and 0.8 V...

  • Page 642: Interrupt Request

    ML62Q1000 Series User's Manual Chapter 20 Analog Comparator (6) Write "0" to the CMPnEN bit to disable the analog comparator operation. (7) The CMPnD bit may be read after "0" is written to the CMPnEN bit because the CMPnD bit holds the comparison result at the time when "0"...
  • Page 643 ML62Q1000 Series User's Manual Chapter 20 Analog Comparator Sampling clock System clock Analog output Comparison result display bit CMPnD Interrupt CMPnINT Interrupt request bit QCMPn Figure 20-5 Analog Comparator Interrupt Generation Timing (with Sampling, When Rising-edge Interrupt Mode is chosen)
  • Page 644 Chapter 21 D/A Converter...

  • Page 645: D/A Converter

    21. D/A Converter 21.1 Features ML62Q1000 series has one channel 8-bit resolution D/A converter that converts digital input signals to analog signals. The number of D/A converter channels is dependent of the product specification. Table 21-1 shows the number of channels.
  • Page 646 ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.1.1 Features · 8-bit resolution · R−2R ladder method · Analog output voltage (DACOUT0/DACOUT1) Output voltage : V x (Setting value in the SFR) / 256 Output impedance : Approx. 6kΩ (Typ.)

  • Page 647: Configuration

    ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.1.2 Configuration Figure 21-1 shows the configuration of the D/A converter. D/A Converter 0 D/A Converter 1 DACCODE1[7:0] DACCODE[7:0] R-2R R-2R DACOUT1 DACOUT0 Ladder Ladder DAEN1 DAEN DACCODE1 DACCON1 DACCODE DACCON Data Bus...

  • Page 648: List Of Pins

    ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.1.3 List of Pins The I/O pins of the D/A converter are assigned to the shared function of the general ports. For details of pin assignment, see Chapter 17 "GPIO". Pin name...

  • Page 649: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.2 Description of Registers 21.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF860 D/A converter 0 control register DACCON 0x00 0xF861 Reserved 0x00 0xF862 D/A converter 0 code register...

  • Page 650: D/A Converter 0 Control Register (Daccon)

    ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.2.2 D/A Converter 0 Control Register (DACCON) DACCON is a special function register (SFR) used to control the D/A converter 0. Address: 0xF860 (DACCON) Access: Access size: 8bit Initial value: 0x00 Word...

  • Page 651: D/A Converter 0 Code Register (Daccode)

    ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.2.3 D/A Converter 0 Code Register (DACCODE) DACCODE is a special function register (SFR) used to set the conversion value of the D/A converter 0. Address: 0xF862 (DACCODE) Access: Access size: 8bit...

  • Page 652: D/A Converter 1 Control Register (Daccon1)

    ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.2.4 D/A Converter 1 Control Register (DACCON1) DACCON1 is a special function register (SFR) used to control the D/A converter 1. Address: 0xF868 (DACCON1) Access: Access size: 8bit Initial value: 0x00 Word...

  • Page 653: D/A Converter 1 Code Register (Daccode1)

    ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.2.5 D/A Converter 1 Code Register (DACCODE1) DACCODE1 is a special function register (SFR) used to the conversion value of the D/A converter 1. Address: 0xF86A (DACCODE1) Access: Access size: 8bit Initial value:...

  • Page 654: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 21 D/A Converter 21.3 Description of Operation 21.3.1 D/A Converter Operation Figure 21-2 shows a process flow chart to control the D/A converter n. Figure 21-3 shows the operation timing chart. Start (1) Set the general-purpose port assigned for DACOUTn pin to the primary function and high-impedance.

  • Page 655: Voltage Level Supervisor

    Chapter 22 Voltage Level Supervisor...

  • Page 656: General Description

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22. Voltage Level Supervisor 22.1 General Description ML62Q1000 series has the Voltage Level Supervisor (VLS0) that detects whether the voltage level of VDD is lower or higher than the specified threshold voltage. FEUL62Q1000 22-1...

  • Page 657: Features

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.1.1 Features · Accuracy: ±4 % · Threshold voltage: Selectable from 12 values (1.85 to 4.00 V) · Operation mode: Supervisor mode (continuous detection) or single mode (one detection) mode Description Detect the voltage level of V only once.

  • Page 658: Configuration

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.1.2 Configuration The voltage level supervisor (VLS0) consists of a comparator, a sampling control circuit, and a low level detection control circuit. Figure 22-1 shows the configuration of the VLS0. LSCLK...

  • Page 659: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.2 Description of Registers 22.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF850 Voltage level supervisor 0 control register VLS0CON 0x00 0xF851 Reserved 0x00 0xF852 Voltage level supervisor 0 mode register...

  • Page 660: Voltage Level Supervisor 0 Control Register (Vls0Con)

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.2.2 Voltage Level Supervisor 0 Control Register (VLS0CON) VLS0CON is a special function register (SFR) used to control the VLS0(Voltage Level Supervisor). This register is unresetable by anything other than the Power On Reset(POR) and RESETN pin reset.

  • Page 661: Voltage Level Supervisor 0 Mode Register (Vls0Mod)

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.2.3 Voltage Level Supervisor 0 Mode Register (VLS0MOD) VLS0MOD is a special function register (SFR) used to control the operation mode of the VLS0(Voltage Level Supervisor). Set this register only when the VLS0 is stopped (VLS0EN bit of VLS0CON register is "0").
  • Page 662 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor [Note] Ÿ There is a limitation in each mode for entering the STOP/STOP-D mode while the VLS0 is runing. Mode Description The VLS0 is running in the The MCU can enter the STOP/STOP-D mode only when the supervisor mode VLS0RF bit is "1".

  • Page 663: Voltage Level Supervisor 0 Level Register (Vls0Lv)

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.2.4 Voltage Level Supervisor 0 Level Register (VLS0LV) VLS0LV is a special function register (SFR) used to set the detection voltage. Set this register only when the VLS0 is stopped (VLS0EN bit of VLS0CON register is "0").

  • Page 664: Voltage Level Supervisor 0 Sampling Register (Vls0Smp)

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.2.5 Voltage Level Supervisor 0 Sampling Register (VLS0SMP) VLS0SMP is a special function register (SFR) used to control sampling the voltage level detection. Set this register only when the VLS0 is stopped (VLS0EN bit of VLS0CON register is "0").

  • Page 665: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.3 Description of Operation VLS0 can be used to verify if V is lower or higher than the specified threshold voltage. In addition, by using VLS0, a VLS0 interrupt can be generated when V is lower than the threshold voltage, or a VLS0 reset can be generated.

  • Page 666: Supervisor Mode

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.3.1 Supervisor Mode In the supervisor mode, the voltage level of V can be constantly detected. This mode is suitable for using the interrupt/reset when the low voltage is detected. Figure 22-2 shows the flow chart for starting the VLS in the supervisor mode.
  • Page 667 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.3.1.1 Reset Output Figure 22-3 shows the operation timing chart when the VLS0 reset output without sampling is specified. (1)~(5) ↓ ↓ ↓ ↓ ↓ VLS0EN bit VLS0RF Threshold voltage (at rise)
  • Page 668 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor Figure 22-4 shows the operation timing chart when the VLS0 reset output with sampling is specified. (1)~(5) (10) (11) ↓ ↓ ↓ ↓ ↓ ↓ ↓ VLS0EN bit VLS0RF Threshold voltage (at rise)
  • Page 669 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.3.1.2 Interrupt Output Figure 22-5 shows an example of the operation timing chart when the VLS0 interrupt output without sampling is specified. (1)~(5) ↓ ↓ ↓ ↓ ↓ VLS0EN bit VLS0RF...
  • Page 670 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor Figure 22-6 shows an example of the operation timing chart when the VLS0 interrupt output with sampling is specified. (1)~(5) (10) (11) (12) ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓...

  • Page 671: Single Mode

    ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.3.2 Single Mode In the single mode, the software waits for the VLS0 interrupt to detect the voltage. It is useful for intermittently checking Figure 22-7 shows the flow chart for starting the VLS in the single mode.
  • Page 672 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.3.2.1 Single mode 1 The single mode 1 always generates the interrupt at completing the detection. Figure 22-8 shows an example of the operation timing diagram without sampling in single mode 1.
  • Page 673 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor Figure 22-9 shows an example of the operation timing diagram with sampling in single mode 1. (1)~(5) ↓ ↓ ↓ ↓ VLS0EN bit VLS0RF Threshold voltage VLSF VLS0 comparator comparison result...
  • Page 674 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor 22.3.2.2 Single mode 2 The single mode 2 generates the interrupt when the V is lower than the threshold voltage. Figure 22-10 shows an example of the operation timing diagram without sampling in single mode 2.
  • Page 675 ML62Q1000 Series User's Manual Chapter 22 Voltage Level Supervisor Figure 22-11 shows an example of the operation timing diagram with sampling in single mode 2. (1)~(5) ↓ ↓ ↓ ↓ VLS0EN bit VLS0RF Threshold voltage VLSF VLS0 comparator comparison result...

  • Page 676: Successive Approximation Type A/D Converter

    Chapter 23 Successive Approximation Type A/D Converter...

  • Page 677: General Description

    23. Successive Approximation Type A/D Converter 23.1 General Description ML62Q1000 series has the Successive Approximation type A/D Converter (SA-ADC), converts an analog input level to a digital value. The number of A/D Converter channels is dependent of the product specification.

  • Page 678: Features

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.1.1 Features · Resolution : 10bit · Conversion time : Min. 2.25μs/channel (conversion clock is 8MHz) · Number of input channel : Max. 16ch · Reference voltage: Voltage input from the V pin, Internal reference voltage(approx.1.55V) or External reference...

  • Page 679: Configuration

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.1.2 Configuration Figure 23-1 shows the configuration of SA-ADC. Successive approximation Selector type A/D convertor SADR SADRn 1.55V SADINT SADLMOD Reference AIN0 SADUPL voltage SADLOL AIN15 Regulator Selector Selector...
  • Page 680 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.1.3 List of Pins The I/O pins of the Successive Approximation type A/D converter are assigned to the shared function of the general ports. For details of pin assignment, see Chapter 17 "GPIO".
  • Page 681 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter Table 23-2 shows the list of the general ports used for the A/D Converter and the register settings of the ports. Table 23-2 Ports used in the A/D Converter and the register settings...
  • Page 682 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2 Description of Registers 23.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF800 SADR0L 8/16 0x00 SA-ADC result register 0 SADR0 0xF801 SADR0H 0x00 0xF802...
  • Page 683 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter Symbol Initial Address Name Size Value Byte Word 0xF828 SADMODL 8/16 0x00 SA-ADC mode register SADMOD 0xF829 SADMODH 0x00 0xF82A SADCONL 8/16 0x00 SA-ADC control register SADCON 0xF82B SADCONH...

  • Page 684: Sa-Adc Result Register N (Sadrn : N=0 To 15, 16)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.2 SA-ADC Result Register n (SADRn : n=0 to 15, 16) SADRn is a special function register (SFR) used to store the SA-ADC conversion results on channels 0 to 15 and channel 16 (temperature sensor).

  • Page 685: Sa-Adc Result Register (Sadr)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.3 SA-ADC Result Register (SADR) SADR is a read-only special function register (SFR) used to store the A/D conversion results on channels 0 to 15, 16 (temperature sensor) and 17 (A/D converter test function).

  • Page 686: Sa-Adc Upper/Lower Limit Status Register 0 (Saduls0)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.4 SA-ADC Upper/Lower Limit Status Register 0 (SADULS0) SAULS0 is a special function register (SFR) used to indicate whether the A/D conversion result matches to the condition of upper/lower limit.

  • Page 687: Sa-Adc Upper/Lower Limit Status Register 1 (Saduls1)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.5 SA-ADC Upper/Lower Limit Status Register 1 (SADULS1) SAULS1 is a special function register (SFR) used to indicate whether the A/D conversion result matches to the condition of upper/lower limit on channel 16.

  • Page 688: Sa-Adc Mode Register (Sadmod)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.6 SA-ADC Mode Register (SADMOD) SADMOD is a special function register (SFR) used to set the operation mode and operating clock frequency of the A/D converter. The bit symbol "rsvd" means a reserved bit, write "0" to those bits.

  • Page 689: Sa-Adc Control Register (Sadcon)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.7 SA-ADC Control Register (SADCON) SADCON is a special function register (SFR) used to control the operation of the A/D converter. Address: 0xF82A(SADCONL/SADCON), 0xF82B(SADCONH) Access: Access size: 8/16bit Initial value:...

  • Page 690: Sa-Adc Enable Register 0 (Saden0)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.8 SA-ADC Enable Register 0 (SADEN0) SADEN0 is a special function register (SFR) used to choose channels of the A/D converter and enable/disable the conversion. Address: 0xF82C(SADEN0L/SADEN0), 0xF82D(SADEN0H) Access:...

  • Page 691: Sa-Adc Enable Register 1 (Saden1)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.9 SA-ADC Enable Register 1 (SADEN1) SADEN1 is a special function register (SFR) used to choose channels of the A/D converter and enable/disable the conversion. Address: 0xF82E(SADEN1L/SADEN1), 0xF82F(SADEN1H) Access:...

  • Page 692: Sa-Adc Conversion Interval Setting Register (Sadstm)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.10 SA-ADC Conversion Interval Setting Register (SADSTM) SADSTM is a special function register (SFR) used to set the interval time in the consecutive scan A/D conversion mode. The interval time is determined by the follwing formula.

  • Page 693: Sa-Adc Upper/Lower Limit Mode Register (Sadlmod)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.11 SA-ADC Upper/Lower Limit Mode Register (SADLMOD) SADLMOD is a special function register (SFR) used to set modes in the A/D conversion result upper/lower limit detection function. Address: 0xF834(SADLMODL/SADLMOD), 0xF835(SADLMODH)

  • Page 694: Sa-Adc Upper Limit Setting Register (Sadupl)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.12 SA-ADC Upper Limit Setting Register (SADUPL) SADUPL is a special function register (SFR) used to set the upper limit of A/D conversion result. Address: 0xF836(SADUPLL/SADUPL), 0xF836(SADUPLH) Access: Access size:...

  • Page 695: Sa-Adc Reference Voltage Control Register (Vrefcon)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.14 SA-ADC Reference Voltage Control Register (VREFCON) VREFCON is a special function register (SFR) used to choose the internal reference voltage operation and control the operation of the temperature sensor,.

  • Page 696: Sa-Adc Interrupt Mode Register (Sadimod)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.15 SA-ADC Interrupt Mode Register (SADIMOD) SADIMOD is a special function register (SFR) used to choose the interrupt mode of the SA-ADC. Address: 0xF83C(SADIMOD) Access: Access size: 8bit Initial value:...

  • Page 697: Sa-Adc Trigger Register (Sadtrg)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.16 SA-ADC Trigger Register (SADTRG) SADTRG is a special function register (SFR) used to control the trigger event for the SA-ADC. Address: 0xF83E(SADTRG) Access: Access size: 8bit Initial value:...

  • Page 698: Sa-Adc Test Mode Register (Sadtmod)

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.2.17 SA-ADC test mode register (SADTMOD) SADTMOD is a register (SFR) used to control the SA-ADC test function. This function enables to check if the successive approximation type A/D converter and the analog switch work correctly, by performing the A/D conversion for the full scale, zero scale and the internal reference voltage (approx.

  • Page 699: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.3 Description of Operation 23.3.1 Operation of Successive Approximation Type A/D Converter Figure 23-2 shows a setting example when one-time A/D conversion is performed using channel 1 and 0.
  • Page 700 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter Figure 23-3 shows a setting example when one-time A/D conversion is performed in HALT mode using channel 1 and 0. Setting start Set the ENOSC bit of the FCON register to "1" to start supplying the high-speed clock.
  • Page 701 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter Figure 23-4 shows a setting example when one-time A/D conversion is performed using channel 1 and 0 starting by a trigger event. Setting start Set the ENOSC bit of the FCON register to "1" to start supplying the high-speed clock.
  • Page 702 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter Figure 23-5 shows operation waveforms when one-time A/D conversion is performed using channel 1 and 0. HSCLK/LSCLK SARUN bit A/D converting Conversion time Conversion time A/D conversion on channel 0...

  • Page 703: How To Test The Successive Approximation Type A/D Converter

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter HSCLK/LSCLK SARUN A/D conversion on channel 0 SADULSn SADINT Reflect the Clear the detection Reflect the detection result result by writing “1” detection result to SAULSn bit The figure shows the waveforms when the condition set in SALMD1 to 0 bits satisfied.

  • Page 704: A/D Conversion Time Setting

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.3.3 A/D Conversion Time Setting For the A/D conversion time and sampling time, the conversion time and configurable range vary depending on the following settings: Ÿ Reference voltage set using the reference voltage control register (VREFCON) Ÿ...
  • Page 705 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter Table 23-4 A/D conversion time when using the internal reference voltage as reference voltage Conversion time SADMOD Conversion SAD_CLK clock count SASHT[3:0] 32kHz 0.5MHz 1MHz 2MHz 4MHz 8MHz 427 μs...
  • Page 706 ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter Table 23-6 Sampling time when using the internal reference voltage as reference voltage Sample/ Sampling time SADMOD hold SAD_CLK clock SASHT[3:0] 32kHz 0.5MHz 1MHz 2MHz 4MHz 8MHz count 30 μs...

  • Page 707: Notes On Sa-Adc

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.4 Notes on SA-ADC 23.4.1 Sampling Time Setting Sampling time > 8�� ( �� + �� The SA-ADC sampling time should satisfy the following formula: ������������ : Input impedance of external resistor...

  • Page 708: Noise Suppression

    ML62Q1000 Series User's Manual Chapter 23 Successive Approximation Type A/D Converter 23.4.2 Noise Suppression In order to prevent deterioration in accuracy of A/D conversion, operate the A/D converter in the environment with little noise. The following processes are recommended for noise reduction: - Perform A/D conversion in the HALT mode.
  • Page 709 Chapter 24 Regulator...

  • Page 710: Regulator

    ML62Q1000 Series User's Manual Chapter 24 Regulator 24. Regulator 24.1 General Description ML62Q1700 group incorporates the regulator. Figure 24-1 shows the general scheme of the regulator. The regulator generates a constant internal logic voltage (V ) independent of the variation of V (1.6 V to 5.5 V)

  • Page 711: Features

    ML62Q1000 Series User's Manual Chapter 24 Regulator 24.1.1 Features Mode VDDL voltage STOP mode 1.55 V HALT mode 1.55 V HALT-H mode 1.55 V Program run mode 1.55 V STOP-D mode 1.1 V (content of RAM and SFR can be retained)

  • Page 712: Configuration

    ML62Q1000 Series User's Manual Chapter 24 Regulator 24.1.2 Configuration Figure 24-2 shows the configuration of the internal power supply. =1.6 V to 5.5 V Regulator =1 μF or larger =1.55 V =1 μF Logic Flash Oscillation GPIO memory circuit circuit...

  • Page 713: List Of Pins

    ML62Q1000 Series User's Manual Chapter 24 Regulator 24.1.3 List of Pins via a capacitor (1 μF). In order to stabilize V , connect the V pin to V Pin name Function Positive power supply pin for the internal logic circuits [Note] 1 μF or...
  • Page 714 Chapter 25 Flash Memory...

  • Page 715: Flash Memory

    25. Flash Memory 25.1 General Description ML62Q1000 series has the flash memory in the program memory space and data flash area. For details of the program memory space and data flash area, see Chapter 2 "CPU and Memory Space". The flash memory is programmable by following three ways.
  • Page 716 ML62Q1000 Series User's Manual Chapter 25 Flash Memory The specification of the program memory space and data flash are is dependent of the product. · Program memory space and Data flash area Overview (Size and Address) Program memory space Data flash area...
  • Page 717 ML62Q1000 Series User's Manual Chapter 25 Flash Memory · Program memory space and Data flash area Overview (Functions and Characteristics) Item Program memory space Data flash area Chip erase(ISP only) All area All area ML62Q1300 group: 2K byte Block erase...

  • Page 718: List Of Pins

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.1.1 List of Pins Programming by the ISP function uses the following pins. Signal name Function RESET_N Input signal for entering the ISP mode Input signal for entering the ISP mode and data input/output data in the...

  • Page 719: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2 Description of Registers 25.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF090 FLASHAL 8/16 0xFF Flash address register FLASHA 0xF091 FLASHAH 0xFF 0xF092 FLASHD0L 8/16 0xFF Flash data register 0...

  • Page 720: Flash Address Register (Flasha)

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2.2 Flash Address Register (FLASHA) FLASHA is a special function register (SFR) used to set the erasing and programming address. Address: 0xF090(FLASHAL/FLASHA), 0xF091(FLASHAH) Access: Access size: 8/16bit Initial value: 0xFFFF Word FLASHA...

  • Page 721: Flash Segment Register (Flashseg)

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2.3 Flash Segment Register (FLASHSEG) FLASHSEG is a special function register (SFR) used to set the segment for erasing and programming the flash memry. Address: 0xF09A(FLASHSEG) Access: Access size: 8bit Initial value:...
  • Page 722 ML62Q1000 Series User's Manual Chapter 25 Flash Memory Table 25-2 Address Setting Values for Sector Erase FLASHSEG FLASHA Group Segment Block Address Size register register Sector 0 0x0000 to 0x03FF 1K byte 0x0000 Sector 1 0x0400 to 0x07FF 1K byte...

  • Page 723: Flash Data Register 0 (Flashd0)

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2.4 Flash Data Register 0 (FLASHD0) FLASHD0 is a special function register (SFR) used to set programming data. Address: 0xF092(FLASHD0L/FLASHD0), 0xF093(FLASHD0H) Access: Access size: 8/16bit Initial value: 0xFFFF Word FLASHD0 Byte FLASHD0H...

  • Page 724: Flash Data Register 1 (Flashd1)

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2.5 Flash Data Register 1 (FLASHD1) FLASHD1 is a special function register (SFR) used to set programming data. Address: 0xF094(FLASHD1L/FLASHD1), 0xF095(FLASHD1H) Access: Access size: 8/16bit Initial value: 0xFFFF Word FLASHD1 Byte FLASHD1H...

  • Page 725: Flash Control Register (Flashcon)

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2.6 Flash Control Register (FLASHCON) FLASHCON is a write-only special function register (SFR) used to control the block erase and sector erase for the flash memory. This register always returns 0x00 for reading.

  • Page 726: Flash Acceptor (Flashacp)

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2.7 Flash Acceptor (FLASHACP) FLASHACP is a write-only special function register (SFR) used to accept for erasing/programming the flash memory. Address: 0xF098(FLASHACP) Access: Access size: 8bit Initial value: 0x00 Word Byte FLASHACP...

  • Page 727: Flash Self Register (Flashslf)

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2.8 Flash Self Register (FLASHSLF) FLASHSLF is a special function register (SFR) used to enable erasing and programming the flash memory. Address: 0xF09C(FLASHSLF) Access: Access size: 8bit Initial value: 0x00 Word Byte...

  • Page 728: Flash Status Register (Flashsta)

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.2.9 Flash Status Register (FLASHSTA) FLASHSTA is a read-only special function register (SFR) used to check status of the flash memory. Address: 0xF09E(FLASHSTA) Access: Access size: 8bit Initial value: 0x00 Word Byte...

  • Page 729: Self-Programming

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.3 Self-programming The self-programming is the function to program (erase and program) the program memory space and data flash area using special function registers (SFRs). Table 25-3 shows the self-programming specifications for each of the program memory space and data flash area.

  • Page 730: Programming Program Memory Space

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.3.2 Programming Program Memory Space In the program memory space (flash memory), block erase in units of 16 Kbytes, sector erase in units of 1 Kbyte, and reprogram in units of 4 bytes can be executed.
  • Page 731 ML62Q1000 Series User's Manual Chapter 25 Flash Memory Figure 25-2 shows the flow diagram for programming the program memory space. Start programming Set the high-speed clock for the system clock through the System clock setting FCON register FSELF = 1...

  • Page 732: Programming Data Flash Area

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.3.3 Programming Data Flash Area In the data flash area (flash memory), block erase in units of 2 Kbytes (ML62Q1300 group) or 4 Kbytes (ML62Q1500/1700 group), sector erase in units of 128 bytes, and programming in units of 1 byte can be executed.
  • Page 733 ML62Q1000 Series User's Manual Chapter 25 Flash Memory Figure 25-4 shows the flow diagram for programming the data flash area. Start data flash programming Set the high-speed clock for the system clock through the System clock setting FCON register Interrupt setting, EI If using interrupts, execute MCINTEL.2=1, IE2.2=1, and EI.

  • Page 734: Notes On Use Of Self-Programming

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.3.4 Notes on use of self-programming Table 25-5 shows the notes on the use of self-programming (block erase/sector erase/program). Table 25-5 Notes on Use of Self-programming Item Notes System clock during use of Set to HSCLK.

  • Page 735: In-System Programming Function

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.4 In-System Programming Function The In-System Programming (ISP) function is used to program a program memory space or data flash area through UART communication with an external device. 25.4.1 Programming Procedure Figure 25-5 shows the flow diagram for programming the flash memory using the ISP function.

  • Page 736: Communication Command

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.4.3 Communication Command 3-byte commands are used to make the communication in the ISP function. Table 25-7 shows the ISP mode commands. Table 25-7 ISP Mode Command List Command Fist byte Second byte...

  • Page 737: Transition Command To Isp Mode

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.4.4 Transition Command to ISP Mode Figure 25-6 shows the timing diagram for transition to the ISP mode. RESET_N Stop bit Start bit TEST0 Min.1μs 0x80 Write Min.100μs Min.14ms Min.250μs Min.100μs Min.250μs Min.2ms...

  • Page 738: Flash Memory Handling

    ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.4.5 Flash Memory Handling Figure 25-7 shows the flow diagram for erasing/programming the flash memory after transition to the ISP mode. Start ISP Initial setting See Section 25.4.5.1 "Initial Setting" for details.
  • Page 739 ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.4.5.1 Initial Setting Figure 25-8 shows the initial setting flow. The flash memory erase/program protection is released at the time of initial setting. Start initial setting Initial setting command transmission (1) Command transmission completion...
  • Page 740 ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.4.5.2 Erasing Specified Flash Memory Area Figure 25-9 shows the flow diagram for erasing the specified flash memory area. Start erase Enable the erase/write/verify using the commands. Initial setting command transmission (6) Not required if it is already enabled.
  • Page 741 ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.4.5.3 Programming to Specified Flash Memory Area Figure 25-10 shows the flow diagram for programming to the specified flash memory area. Start programming Enable the erase/program/verify using the commands. Initial setting command transmission (6) Not required if it is already enabled.
  • Page 742 ML62Q1000 Series User's Manual Chapter 25 Flash Memory 25.4.5.4 Verifying Specified Flash Memory Area Figure 25-11 shows the flow diagram for verifying the specified flash memory area. Start verify Enable the erase/program/verify using the commands. Initial setting command transmission (6) Not required if it is already enabled.
  • Page 743 Chapter 26 Code Option...

  • Page 744: Code Option

    ML62Q1000 Series User's Manual Chapter 26 Code Option 26. Code Option 26.1 General Description The code option is used to choose the CPU operating mode, PLL reference frequency, watchdog timer operation clock, etc. depending on values written in the code option area of the program memory space.

  • Page 745: Description Of Code Option

    ML62Q1000 Series User's Manual Chapter 26 Code Option 26.2 Description of Code Option 26.2.1 Code Options 0 (CODEOP0) This is the symbol assigned to address in the code option area of the program memory space (different from the special function registers (SFR)).

  • Page 746: Code Options 1 (Codeop1)

    ML62Q1000 Series User's Manual Chapter 26 Code Option 26.2.2 Code Options 1 (CODEOP1) This is the symbol assigned to address in the code option area of the program memory space (different from the special function registers (SFR)). Address: (See Table 26-1)

  • Page 747: Code Options 2 (Codeop2)

    ML62Q1000 Series User's Manual Chapter 26 Code Option 26.2.3 Code Options 2 (CODEOP2) This is the symbol assigned to address in the code option area of the program memory space (different from the special function registers (SFR)). Address: (See Table 26-1)

  • Page 748: Code Option Data Setting

    ML62Q1000 Series User's Manual Chapter 26 Code Option 26.3 Code Option Data Setting The address of code option area is dependent of the size of the program memory space (flash memory). Table 26-1 shows addresses of code option areas for each product.
  • Page 749 ML62Q1000 Series User's Manual Chapter 26 Code Option Figure 26-2 shows an example of a code option setting program (for products with the program memory space=64 Kbytes). The setting is described in the start-up file (ML621xxx.ASM) of each product. Set every unused bit of the code option data area to "1".
  • Page 750 Chapter 27 LCD Driver...

  • Page 751: Lcd Driver

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27. LCD driver 27.1 General Description The ML62Q1000 series has the LCD driver that displays the contents of display register onto a LCD panel. 27.1.1 Features · Max.480 dots ML62Q1700/ML62Q1701/ML62Q1702/ML62Q1703/ML62Q1704： 24seg×8com (com Max.), 29seg×3com (seg Max.) ML62Q1710/ML62Q1711/ML62Q1712/ML62Q1713/ML62Q1714：...

  • Page 752: Configuration Of Lcd Display Function

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.1.2 Configuration of LCD Display Function Figure 27-1 shows the configuration of the LCD display function circuit. (*1) COM0 COM7 SEG0 SEG64 Common Segment driver driver Voltage regulator circuit Common control Bias generation...

  • Page 753: Configuration Of Bias Generation Circuit

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.1.3 Configuration of Bias Generation Circuit The bias generation circuit operation is selectable from the following four types. (1) Internal boosting type: Boost the voltage (V ) generated from the internal voltage regulator circuit using the capacitor (C...
  • Page 754 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Voltage regulator circuit OFF LCD control Block Boosting/ dividing circuit ON To LCD driver to V (3) External supply capacitive dividing type Voltage regulator LCD control circuit OFF Block Boosting/ dividing circuit OFF...

  • Page 755: List Of Pins

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.1.4 List of Pins ● : Available -: Unavailable 48pin 52pin 64pin 80pin 100pin product product product product product ML62Q1720/ ML62Q1721/ ML62Q1700/ ML62Q1710/ ML62Q1733/ ML62Q1743/ ML62Q1722/ Function Pin name ML62Q1701/ ML62Q1711/ ML62Q1734/...
  • Page 756 ML62Q1000 Series User's Manual Chapter 27 LCD Driver 48pin 52pin 64pin 80pin 100pin product product product product product ML62Q1720/ ML62Q1721/ ML62Q1700/ ML62Q1710/ ML62Q1733/ ML62Q1743/ ML62Q1722/ Function Pin name ML62Q1701/ ML62Q1711/ ML62Q1734/ ML62Q1744/ ML62Q1723/ ML62Q1702/ ML62Q1712/ ML62Q1735/ ML62Q1745/ ML62Q1724/ ML62Q1703/ ML62Q1713/...
  • Page 757 ML62Q1000 Series User's Manual Chapter 27 LCD Driver 48pin 52pin 64pin 80pin 100pin product product product product product ML62Q1720/ ML62Q1721/ ML62Q1700/ ML62Q1710/ ML62Q1733/ ML62Q1743/ ML62Q1722/ Function Pin name ML62Q1701/ ML62Q1711/ ML62Q1734/ ML62Q1744/ ML62Q1723/ ML62Q1702/ ML62Q1712/ ML62Q1735/ ML62Q1745/ ML62Q1724/ ML62Q1703/ ML62Q1713/...

  • Page 758: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2 Description of Registers 27.2.1 List of Registers Initial Address Name Symbol(Byte) Symbol(Word) Size Value 0xF0F0 BIASCONL 8/16 0x08 Bias control register BIASCON 0xF0F1 BIASCONH 0x00 0xF0F2 DSPMODL 8/16 0x40 Display mode register...

  • Page 759: Bias Control Register(Biascon)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.2 Bias Control Register(BIASCON) BIASCON is a special function register (SFR) to adjust the display contrast in 32 levels in the internal boosting mode. BIASCONL is a special function register (SFR) used to control the bias generation circuit.
  • Page 760 ML62Q1000 Series User's Manual Chapter 27 LCD Driver 111: 1/128 LSCLK(256Hz) BSON This bit is used to control the bias generation circuit operation. Setting the BSON bit to "1" generates the LCD driving voltages (VL1 to VL3 ). Bias generation circuit turns off (initial value)

  • Page 761: Display Mode Register(Dspmod)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.3 Display Mode Register (DSPMOD) DSPMODH is a special function register (SFR) to control the LCD driver waveform type. DSPMODL is a special function register (SFR) to control the LCD driver frame frequency and duty.

  • Page 762: Display Control Register(Dspcon)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.4 Display Control Register (DSPCON) DSPCON is a special function register (SFR) to control the display mode. Address: 0xF0F4 Access: Access size: 8/16 bits Initial value: 0x0000 Word DSPCON Byte DSPCONH DSPCONL −...

  • Page 763: Segment Mode Register0 (Segmod0)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.5 Segment Mode Register 0 (SEGMOD0) SEGMOD0 is a specific function register (SFR) to select the SEG15 to SEG0 functions. Address: 0xF0F6 Access: Access size: 8/16 bits Initial value: 0x0000 Word SEGMOD0...
  • Page 764 ML62Q1000 Series User's Manual Chapter 27 LCD Driver S3MD This bit is used to select the general-purpose input/output and segment output functions. 0: P12 (Initial value) 1: SEG3 S2MD This bit is used to select the general-purpose input/output and segment output functions.

  • Page 765: Segment Mode Register1 (Segmod1)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.6 Segment Mode Register 1(SEGMOD1) SEGMOD1 is a specific function register (SFR) to select the SEG31 to SEG16 functions. Address: 0xF0F8 Access: Access size: 8/16 bits Initial value: 0x0000 Word SEGMOD1 Byte...
  • Page 766 ML62Q1000 Series User's Manual Chapter 27 LCD Driver S19MD This bit is used to select the general-purpose input/output and segment output functions. 0: PA2 (Initial value) 1: SEG19 S18MD This bit is used to select the general-purpose input/output and segment output functions.

  • Page 767: Segment Mode Register2 (Segmod2)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.7 Segment Mode Register 2(SEGMOD2) SEGMOD2 is a specific function register (SFR) to select the SEG47 to SEG32 functions. Address: 0xF0FA Access: Access size: 8/16 bits Initial value: 0x0000 Word SEGMOD2 Byte...
  • Page 768 ML62Q1000 Series User's Manual Chapter 27 LCD Driver S35MD This bit is used to select the general-purpose input/output and segment output functions. 0: P57 (Initial value) 1: SEG35 S34MD This bit is used to select the general-purpose input/output and segment output functions.

  • Page 769: Segment Mode Register3 (Segmod3)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.8 Segment Mode Register 3(SEGMOD3) SEGMOD3 is a specific function register (SFR) to select the SEG63 to SEG48 functions. Address: 0xF0FC Access: Access size: 8/16 bits Initial value: 0x0000 Word SEGMOD3 Byte...
  • Page 770 ML62Q1000 Series User's Manual Chapter 27 LCD Driver S51MD This bit is used to select the general-purpose input/output and segment output functions. 0: P32 (Initial value) 1: SEG51 S50MD This bit is used to select the general-purpose input/output and segment output functions.

  • Page 771: Segment Mode Register4 (Segmod4)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.9 Segment Mode Register 4 (SEGMOD4) SEGMOD4 is a specific function register (SFR) to select the SEG64 functions. Address: 0xF0FE Access: Access size: 8/16 bits Initial value: 0x0000 Word SEGMOD4 − Byte...

  • Page 772: Display Register(Dspr00 To Dspr64)

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.2.10 Display Register (DSPR00 to DSPR64) DSPR00 to DSPR64 are special function registers (SFR) to store display data. As the initial value of thease registers are undefined, set data to determine the contents of display.
  • Page 773 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Table 27-1 shows a list of registers available for each product. " " "-" means the register does not exist and writing to register is invalid and is read. Table 27-1 List of Display Registers ●...
  • Page 774 ML62Q1000 Series User's Manual Chapter 27 LCD Driver 48pin 52pin 64pin 80pin 100pin product product product product product ML62Q1720/ ML62Q1721/ Correspon ML62Q1700/ ML62Q1710/ ML62Q1733/ ML62Q1743/ Register ML62Q1722/ Address ding ML62Q1701/ ML62Q1711/ ML62Q1734/ ML62Q1744/ name ML62Q1723/ segment ML62Q1702/ ML62Q1712/ ML62Q1735/ ML62Q1745/...

  • Page 775: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.3 Description of Operation 27.3.1 Operation of LCD Driver Circuit LCD Figure 27-3 shows the LCD driver circuit operation. System reset Operating state Reset Operating state BIASCON.BSON LCD bias voltage LCD bias voltage generated...

  • Page 776: Common Output Waveform

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.3.3 Common Output Waveform Figure 27-5 shows the waveform A output from the common pins in 1/3 duty mode. Frame COM0 COM1 COM2 Figure 27-5 Waveform A Output from Common Pins in 1/3 Duty Figure 27-6 shows the waveform A output from the common pins in 1/4 duty mode.
  • Page 777 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Figure 27-7 shows the waveform B output from the common pins in 1/3 duty mode. Frame COM0 COM1 COM2 Figure 27-7 Waveform B Output from Common Pins in 1/3 Duty Figure 27-8 shows the waveform B output from the common pins in 1/4 duty mode.

  • Page 778: Segment Output Waveform

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.3.4 Segment Output Waveform Figure 27-9 shows the waveform A output from the segment pins in 1/3 duty mode. Frame Data SEGn Data SEGn Data SEGn Data SEGn ・ ・ ・ ・...
  • Page 779 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Figure 27-10 shows the waveform A output from the segment pins in 1/4 duty mode. Frame Data SEGn Data SEGn Data SEGn Data SEGn ・ ・ ・ ・ ・ ・ Data SEGn ・...
  • Page 780 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Figure 27-11 shows the waveform B output from the segment pins in 1/3 duty mode. Frame Data SEGn Data SEGn Data SEGn Data SEGn ・ ・ ・ ・ ・ ・ Data SEGn...
  • Page 781 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Figure 27-12 shows the waveform B output from the segment pins in 1/4 duty mode. Frame Data SEGn Data SEGn Data SEGn Data SEGn ・ ・ ・ ・ ・ ・ Data SEGn ・...

  • Page 782: Common Output Waveform For Led Drive

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.3.5 Common Output Waveform for LED drive Figure 27-13 shows the waveform A output from the common pins in 1/3 duty and LED drive mode. Frame COM0 COM1 COM2 Figure 27-13 Waveform A Output from Common Pins in 1/3 Duty and LED drive mode Figure 27-14 shows the waveform A output from the common pins in 1/4 duty and LED drive mode.
  • Page 783 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Figure 27-15 shows the waveform B output from the common pins in 1/3 duty and LED drive mode. Frame COM0 COM1 COM2 Figure 27-15 Waveform B Output from Common Pins in 1/3 Duty and LED drive mode Figure 27-16 shows the waveform B output from the common pins in 1/4 duty and LED drive mode.

  • Page 784: Segment Output Waveform For Led Drive

    ML62Q1000 Series User's Manual Chapter 27 LCD Driver 27.3.6 Segment Output Waveform for LED drive Figure 27-17 shows the waveform A output from the segment pins in 1/3 duty and LED drive mode. Frame Data SEGn Data SEGn Data SEGn...
  • Page 785 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Figure 27-18 shows the waveform A output from the segment pins in 1/4 duty and LED drive mode. Frame Data SEGn Data SEGn Data SEGn Data SEGn ・ ・ ・ ・ ・...
  • Page 786 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Figure 27-19 shows the waveform B output from the segment pins in 1/3 duty and LED drive mode.。 Frame Data SEGn Data SEGn Data SEGn Data SEGn ・ ・ ・ ・ ・...
  • Page 787 ML62Q1000 Series User's Manual Chapter 27 LCD Driver Figure 27-20 shows the waveform B output from the segment pins in 1/4 duty and LED drive mode. Frame Data SEGn Data SEGn Data SEGn Data SEGn ・ ・ ・ ・ ・...

  • Page 788: On-Chip Debug Function

    Chapter 28 On-Chip Debug Function...

  • Page 789: General Description

    This function is used by connecting the host PC and LSI through the on-chip debug emulator EASE1000 (hereafter referred to as "EASE1000") manufactured by LAPIS Semiconductor. On-board debugging or programming is available by using the program development environment software "DTU8 debugger"...

  • Page 790: Features

    ML62Q1000 Series User's Manual Chapter 28 On-Chip Debug Function 28.1.1 Features · The following debug functions are provided using the DTU8 debugger by connecting LSI and EASE1000 − Emulation - Real time emulation - Single step emulation − Break - Hardware break point break (four points)

  • Page 791: Configuration

    ML62Q1000 Series User's Manual Chapter 28 On-Chip Debug Function 28.1.2 Configuration When using the on-chip debug function, two methods are available for power supply to LSI as described below: - Use the 3.3 VOUT power supply (+3.3 V/100 mA) of EASE1000 - Use the power supply of the target system (VDD=1.6 V to 5.5 V)

  • Page 792: List Of Pins

    ML62Q1000 Series User's Manual Chapter 28 On-Chip Debug Function 28.1.3 List of Pins The following pins are used for the on-chip debug function. Signal name Function RESET_N On-chip debug function signal input P00/TEST0 On-chip debug function signal output FEUL62Q1000 28-4...

  • Page 793: How To Use On-Chip Debug Function

    ML62Q1000 Series User's Manual Chapter 28 On-Chip Debug Function 28.2 How to Use On-chip Debug Function See "DTU8 User's Manual" for how to use the on-chip debug function using EASE1000 and the DTU8 debugger. See "Flash Multi-Writer MWU16 User's Manual" for how to download a program using EASE1000 and flash multi-writer MWU16.

  • Page 794: Operation Of Peripheral Circuits During Breaks In The On-Chip Debug Mode

    ML62Q1000 Series User's Manual Chapter 28 On-Chip Debug Function 28.4 Operation of Peripheral Circuits during breaks in the on-chip debug mode DTU8 debugger allows users to choose whether to continue or stop operating the peripheral circuits during the break state on the debugger.
  • Page 795 Chapter 29 Safety Function...

  • Page 796: Safety Function

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29. Safety Function 29.1 General Description ML62Q1000 series has the safety functions to make a safe stop in case a failure is detected by executing the self-diagnosis software, available to support IEC60730/60335. 29-1 FEUL62Q1000...

  • Page 797: Features

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.1.1 Features · Safety Functions on the LSI Function Name Description Control by SFR RAM guard Protest the miss-writing to the RAM Available SFR guard Protest the miss-writing to the SFR Available...

  • Page 798: Description Of Registers

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2 Description of Registers 29.2.1 List of Registers Symbol Initial Address Name Size Value Byte Word 0xF0B0 RAM Guard Setting Register 0 RAMGD 0x00 0xF0B1 Reserved 0x00 0xF0B2 Reserved 0x00 0xF0B3 Reserved...

  • Page 799: Ram Guard Setting Register (Ramgd)

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2.2 RAM Guard Setting Register (RAMGD) RAMGD is a special function register (SFR) used to disable writing the RAM by the CPU and the DMA Controller. Data in the specified RAM area is protectable.

  • Page 800: Sfr Guard Setting Register 0 (Sfrgd0)

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2.3 SFR Guard Setting Register 0 (SFRGD0) SFRGD0 is a special function register (SFR) used to disable writing the SFR by the CPU and the DMA Controller. Data in the specified SFR area is protectable.

  • Page 801: Sfr Guard Setting Register 1 (Sfrgd1)

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2.4 SFR Guard Setting Register 1 (SFRGD1) SFRGD0 is a special function register (SFR) used to disable writing the SFR by the CPU and the DMA Controller. Data in the specified SFR area is protectable.
  • Page 802 ML62Q1000 Series User's Manual Chapter 29 Safety Function Bit symbol Description name SGD14 This bit is used to disable SFRs related to the port 4 described in Chapter 17 "General Purpose Port". The SFR is writable and readable (Initial value)

  • Page 803: Ram Parity Setting Register (Rasfmod)

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2.5 RAM Parity Setting Register (RASFMOD) RASFMOD is a special function register (SFR) used to control the RAM parity error reset function. The RAM parity error is detectable and the RAM parity error reset is generatable.

  • Page 804: Communication Test Setting Register (Comft0)

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2.6 Communication Test Setting Register (COMFT0) COMFT0 is a special function register (SFR) used to control the communication test function, which enables the loop back test with transmit data in the serial communication units. See Section 29.3.1 "Communication Function Self Test"...

  • Page 805: Mcu Status Interrupt Enable Register (Mcintel)

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2.7 MCU Status Interrupt Enable Register (MCINTEL) MCINTEL is a special function register (SFR) used to control enabling/disabling three types of interrupt status on the microcontroller. Address: 0xF050 (MCINTEL) Access: Access size:...

  • Page 806: Mcu Status Interrupt Register (Mcistatl)

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2.8 MCU Status Interrupt Register (MCISTATL) MCISTATL is a read-only special function register (SFR) used to indicate status of the three types of interrupts. The MCI2S bit to MCI0S bit is reset to "0" by writing "1" to the same number of bit in the MCINTCL register.

  • Page 807: Mcu Status Interrupt Clear Register (Mcintcl)

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.2.9 MCU Status Interrupt Clear Register (MCINTCL) MCINTCL is a write-only special function register (SFR) used to clear the MCU status interrupts. If the MCI2C bit to MCI0C bit is set to "1", the interrupt request indicated by the same number of bit in the MCISTATL register gets cleared.

  • Page 808: Description Of Operation

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.3 Description of Operation 29.3.1 Communication Function Self-Test This self test is enabled by the COMFT0 register setting. The communication function can be tested through the self test by internally connecting transmit and receive data of UART and SSIO (synchronous serial port) of the serial communication unit.

  • Page 809: Unused Rom Area Access Reset Function

    : 0x0:0FFC0H to 0x7:0FFFFH ML62Q1721/ML62Q1711/ML62Q1701 : 0x0:0BFC0H to 0x7:0FFFFH ML62Q1720/ML62Q1710/ML62Q1700 : 0x0:07FC0H to 0x7:0FFFFH [Note] " " " ". Ÿ CSR[3] is unused on the ML62Q1000 series. The data of CSR 0x8 to 0xF are handled as 0x0 to 0x7 29-14 FEUL62Q1000...

  • Page 810: Clock Mutual Monitoring Function

    ML62Q1000 Series User's Manual Chapter 29 Safety Function 29.3.3 Clock Mutual Monitoring Function This function monitors if the low-speed clock (low-speed RC oscillation circuit) and high-speed clock (PLL oscillation circuit) are normally oscillating. The 16-bit timer and functional timer can be used to confirm the oscillation.
  • Page 811 ML62Q1000 Series User's Manual Chapter 29 Safety Function Start setting Set the following items through the TMHnMOD register of the 16-bit timer n. - THnOST bit=0 (initial value): Repeat mode 16-bit timer operation - THn8BM bit=0 (initial value): 16-bit timer mode...

  • Page 812: Crc Calculation

    ML62Q1000 Series User's Manual Chapter 29 Safety Function [Note] Ÿ For "Overflow value setting" in Figure 29-4, set the value so that the overflow period of the 16-bit timer n is to be shorter than that of the functional timer n.
  • Page 813 Appendix A...

  • Page 814: Appendix A Register List

    ML62Q1000 Series User’s Manual Appendix A Register List Appendix A Register List Symbol Initial Address Name Size value Byte Word − 0xF000 Data segment register 0x00 0xF001 Reserved 0xF002 FHCKMODL 8/16 0x00 High-speed clock mode register FHCKMOD 0xF003 FHCKMODH 0x44...
  • Page 815 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF030 Interrupt level control enable register ILEN 8/16 0x00 0xF031 Reserved 0x00 0xF032 Current interrupt level management register 8/16 0x00 0xF033 Reserved 0x00 0xF034...
  • Page 816 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF064 Simplified RTC Time Base Counter register LTBRR 0x00 0xF065 Reserved 0x00 Low-speed Time Base Counter Frequency 0xF066 LTBADJL 0x00 Adjustment register L LTBADJ...
  • Page 817 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word Reserved 0x00 0xF0AF 0xF0B0 RAM guard setting register 0 RAMGD 0x00 0xF0B1 Reserved 0x00 0xF0B3 0xF0B4 SFR guard setting register 0L SFRGD0L 8/16 0x00...
  • Page 818 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF0DC CRC Mode Register CRCMOD 0x00 0xF0DD Reserved 0x00 0xF0E3 Expanded external interrupt control register 0 0xF0E4 EEICON0L 8/16 0x00 EEICON0 Expanded external interrupt control register...
  • Page 819 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 不定 0xF10F Display register 15 DSPR15 不定 0xF110 Display register 16 DSPR16 DSPRW16 8/16 不定 0xF111 Display register 17 DSPR17 不定 0xF112 Display register 18...
  • Page 820 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 不定 0xF140 Display register 64 DSPR64 DSPRW64 8/16 0xF141 Reserved 0xF1FF 0xF200 P0DI 8/16 0xFF Port 0 data register 0xF201 P0DO 0x00 0xF202 P0MOD0...
  • Page 821 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF22D P2PSLH 0x00 0xF22E 0x00 Reserved 0xF22F 0x00 0xF230 P3DI 8/16 0xFF Port 3 data register 0xF231 P3DO 0x00 0xF232 P3MOD0 8/16 0x00 Port 3 mode register 01...
  • Page 822 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF265 P6MOD3 0x00 0xF266 P6MOD4 8/16 0x00 Port 6 mode register 45 P6MOD45 0xF267 P6MOD5 0x00 0xF268 P6MOD6 8/16 0x00 Port 6 mode register 67...
  • Page 823 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF2A2 PAMOD0 8/16 0x00 Port A mode register 01 PAMOD01 0xF2A3 PAMOD1 0x00 0xF2A4 PAMOD2 8/16 0x00 Port A mode register 23 PAMOD23 0xF2A5...
  • Page 824 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF312 16-bit timer 1 counter register L TMH1CL 8/16 0x00 TMH1C 0xF313 16-bit timer 1 counter register H TMH1CH 0x00 0xF314 16-bit timer 2 counter register L...
  • Page 825 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF343 16-bit timer 1 interrupt clear register H TMH1ICH 0x00 0xF344 16-bit timer 2 interrupt clear register L TMH2ICL 8/16 0x00 TMH2IC 0xF345 16-bit timer 2 interrupt clear register H...
  • Page 826 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF41B FTM5 event A register H FT5EAH 0x00 0xF41C FTM6 event A register L FT6EAL 8/16 0x00 FT6EA 0xF41D FTM6 event A register H...
  • Page 827 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF44C FTM6 counter register L FT6CL 8/16 0x00 FT6C 0xF44D FTM6 counter register H FT6CH 0x00 0xF44E FTM7 counter register L FT7CL 8/16 0x00...
  • Page 828 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF47D FTM6 clock register H FT6CLKH 0x00 0xF47E FTM7 clock register L FT7CLKL 8/16 0x00 FT7CLK 0xF47F FTM7 clock register H FT7CLKH 0x00 0xF480...
  • Page 829 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF4AE FTM7 interrupt enable register L FT7INTEL 8/16 0x00 FT7INTE 0xF4AF FTM7 interrupt enable register H FT7INTEH 0x00 0xF4B0 FTM0 interrupt status register L...
  • Page 830 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF5FF Serial communication unit 0 transmit/receive 0xF600 SD0BUFL 8/16 0x00 buffer L SD0BUF Serial communication unit 0 transmit/receive 0xF601 SD0BUFH 0x00 buffer H 0xF602...
  • Page 831 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF62F UART10 baud rate register H UA10BRTH 0xFF 0xF630 UART10 baud rate adjustment register UA10BRC 0x00 0xF631 Reserved 0x00 0xF632 UART10 status register UA10STAT...
  • Page 832 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF662 Serial communication unit 3 mode register SU3MOD 0x00 0xF663 Reserved 0x00 Serial communication unit 3 transmission 0xF664 SU3DLYL 0x00 interval setting register L...
  • Page 833 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF693 Reserved 0x00 0xF694 UART41 mode register L UA41MODL 8/16 0x00 UA41MOD 0xF695 UART41 mode register H UA41MODH 0x00 0xF696 UART41 baud rate register L...
  • Page 834 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF6C7 Reserved 0xF6C8 C bus 0 control register (master) I2UM0CON 0x00 0xF6C9 Reserved 0xF6CA C bus 0 mode register L (master) I2UM0MDL I2UM0MOD 8/16...
  • Page 835 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF6FE Reserved 0xF6FF Reserved 0xF700 DMA channel 0 transfer mode register L DC0MODL 8/16 0x00 DC0MOD 0xF701 DMA channel 0 transfer mode register H...
  • Page 836 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF810 SADR8L 8/16 0x00 SA-ADC result register 8 SADR8 0xF811 SADR8H 0x00 0xF812 SADR9L 8/16 0x00 SA-ADC result register 9 SADR9 0xF813 SADR9H 0x00...
  • Page 837 ML62Q1000 Series User’s Manual Appendix A Register List Symbol Initial Address Name Size value Byte Word 0xF841 Reserved 0x00 0xF842 Comparator 0 mode register L CMP0MODL 8/16 0x00 CMP0MOD 0xF843 Comparator 0 mode register H CMP0MODH 0x00 0xF844 Reserved 0x00...

  • Page 838: Appendix B Package Dimensions

    ML62Q1000 Series User’s Manual Appendix B Package Dimensions Appendix B Package Dimensions 16pin SSOP (Unit : mm) Figure B-1 SSOP16 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 839 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 16pin WQFN (Unit : mm) Figure B-2 WQFN16 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 840 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 20pin TSSOP (Unit : mm) Figure B-3 TSSOP20 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 841 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 24pin WQFN (Unit : mm) Figure B-4 WQFN24 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 842 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 32pin TQFP (Unit : mm) Figure B-5 TQFP32 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 843 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 32pin WQFN (Unit : mm) Figure B-6 WQFN32 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 844 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 48pin TQFP (Unit : mm) Figure B-7 TQFP48 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 845 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 52pin TQFP (Unit : mm) Figure B-8 TQFP52 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 846 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 64pin QFP (Unit : mm) Figure B-9 QFP64 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 847 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 64pin TQFP (Unit : mm) Figure B-10 TQFP64 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 848 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 80pin QFP (Unit : mm) Figure B-11 QFP80 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 849 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 100pin QFP (Unit : mm) Figure B-12 QFP100 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
  • Page 850 ML62Q1000 Series User’s Manual Appendix B Package Dimensions 100pin TQFP (Unit : mm) Figure B-13 TQFP100 Package Dimension [Note] Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

  • Page 851: Appendix C Instruction Execution Cycle

    Appendix C Instruction Execution Cycle Appendix C Instruction Execution Cycle ML62Q1000 series has two CPU operating modes defined as the no wait mode and wait mode, in which there are some cases the insturction execution cycles are different each other.
  • Page 852 ML62Q1000 Series User’s Manual Appendix C Instruction Execution Cycle Arithmetic Instructions Min. execution cycle ROM reference cycle Effect of Effect of DSR Instruction [EA+] No wait No wait access Wait mode Wait mode addressing mode mode #imm7 #imm8 ADDC #imm8...
  • Page 853 ML62Q1000 Series User’s Manual Appendix C Instruction Execution Cycle Load/Store instructions Min. execution cycle ROM reference cycle Effect of Effect of Instruction [EA+] No wait No wait Wait mode Wait mode access addressing mode mode [EA] [EA+] [ERm] 1 / 2...
  • Page 854 ML62Q1000 Series User’s Manual Appendix C Instruction Execution Cycle Control Register Access Instructions Min. execution cycle ROM reference cycle Effect of Effect of Instruction [EA+] No wait No wait Wait mode Wait mode access addressing mode mode #signed8 ECSR EPSW...
  • Page 855 ML62Q1000 Series User’s Manual Appendix C Instruction Execution Cycle PUSH/POP Instructions Min. execution cycle ROM reference cycle Effect of Effect of Instruction [EA+] No wait No wait Wait mode Wait mode access addressing mode mode PUSH 1 / 2 1 / 2...
  • Page 856 ML62Q1000 Series User’s Manual Appendix C Instruction Execution Cycle Coprocessor Data Transfer Instructions Min. execution cycle ROM reference cycle Effect of Effect of Instruction [EA+] No wait No wait Wait mode Wait mode access addressing mode mode [EA] CERn [EA+]...
  • Page 857 ML62Q1000 Series User’s Manual Appendix C Instruction Execution Cycle PSW Access Instructions Min. execution cycle ROM reference cycle Effect of Effect of Instruction [EA+] No wait No wait Wait mode Wait mode access addressing mode mode CPLC Sign Extension Instruction Min.
  • Page 858 ML62Q1000 Series User’s Manual Appendix C Instruction Execution Cycle Multiplication and Division Instructions Min. execution cycle ROM reference cycle Effect of Effect of Instruction [EA+] No wait No wait Wait mode Wait mode access addressing mode mode Interrupts Min. execution cycle...

  • Page 859: Appendix D Application Circuit Example

    ML62Q1000 Sereis User’s Manual Appendix D Application Circuit Example Appendix D Application Circuit Example 5.0V SEG64 EASE1000 LCD panel Interface SEG0 3.3VOUT SDATA TEST0 COM2 RST_OUT/SCK RESET_N COM0 ML62Q1000 Reset IC Series IGBT FTM0N control FTM0P Reference voltage EXI0 GPIO BZ0P EN VDD Sensor...

  • Page 860: Appendix E List Of Notes

    ML62Q1000 Series User’s Manual Appendix E. List of Notes Appendix E. List of Notes This Check List has important notes to prevent commonly-made programming mistakes and frequently overlooked or misunderstood hardware specifications of the LSI. Check each note listed in chapter by chapter when coding or evaluating the program.
  • Page 861 ML62Q1000 Series User’s Manual Appendix E. List of Notes Chapter 3 Reset Function See Section 3.3.1 "Operation of Reset Function". [ ] The voltage level supervisor function is only initialized at a reset input pin reset or power-on reset (POR).
  • Page 862 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 4.2.5 "Software Reset Control Register (SOFTRCON)". [ ] Do not enter the standby mode when the SOFTR bit is "1". Ensure the SOFTR bit is "0" before entering the standby mode.
  • Page 863 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 4.3.8 "Block Control Function". [ ] If the clock supply is only stopped without resetting each peripheral circuit using the block control function, it may cause the output levels of the timer, communication and buzzer pins to be fixed, causing the excess current to flow.
  • Page 864 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 6.2.3 "Low-speed Clock Mode Register (FLMOD)". [ ] Do not change the LOSCM1 bit ad LOSCM0 bit when the ENOSC bit is "1", otherwise the operation is unguaranteed. [ ] Set PADXT0 pin and PADXT1 pin to the Hi-Z output mode when choosing the Low-speed crystal oscillation clock for the low-speed clock.
  • Page 865 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 7.2.3 "Low Speed Time Base Register Control Register (LTBCCON)". [ ] Enable the high-speed clock (HSCLK) when using the virtual frequency adjustment mode. [ ] It takes max. two clocks of low-speed clock (LSCLK) from the timing of write the TBRUN bit to the timing of start or stop the operation.
  • Page 866 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 8.2.7 "16-Bit Timer Start Register (TMHSTR)". [ ] The bit 15 to 8 of TMHSTR register are not used in the 16-bit timer mode. Writing “1” to those bits are ignored.
  • Page 867 ML62Q1000 Series User’s Manual Appendix E. List of Notes [ ] The pulse input to the EXTRG0 to EXTRG7 pin must have "the noise removal width chosen by FTnTRF2 to 0 bits of FTnTRG1 register + two timer clocks" or longer.
  • Page 868 ML62Q1000 Series User’s Manual Appendix E. List of Notes Chapter 11 Serial Communication Unit See Section 11.2.2 "Serial Communication Unit n Transmit/Receive Buffer (SDnBUF)". [ ] In the half-duplex communication mode of UART, be sure to choose the transmission mode by setting Un0IO and Un1IO bit of the UARTn mode register (UAn0MOD, UAn1MOD) before writing the transmission data to SDnBUFL and SDnBUFH.
  • Page 869 ML62Q1000 Series User’s Manual Appendix E. List of Notes [ ] When an error occurs in the start bit, the state returns to the reception waiting state. [ ] Do not write the Un1FER bit, Un1OER bit, Un1PER bit and Un1FUL bit by using the bit symbol. Write them by the byte-access.
  • Page 870 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 12.2.7 "I C Bus 0 Mode Register (Master) (I2UM0MOD)". [ ] When using the high-speed clock for the I2C operation, specify the following I2C operating clock frequency depending on the mode and the reference frequency of the PLL oscillation.
  • Page 871 ML62Q1000 Series User’s Manual Appendix E. List of Notes [ ] When performing the software trigger by setting the DCnSTRG bit to "1", the transfer is held if the next instruction is data memory access. Place two NOP instructions after setting DCnSTRG to "1" to prevent the hold and make the immediate transfer.
  • Page 872 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 15.3.5.1 "Buzzer Output Start and Stop Timing". [ ] An error to a maximum of one clock of the low-speed clock (LSCLK) occurs by the time the buzzer output is started after writing "1" to the BZ0RUN bit of the BZ0CON register.
  • Page 873 ML62Q1000 Series User’s Manual Appendix E. List of Notes Chapter 18 External Interrupt Function See Section 18.2.3 "External Interrupt Mode Register 0 (EIMOD0)". [ ] In the STOP/STOP-D/HALT-H(*1) mode, no sampling is performed regardless of the values set in PI7SM to PI0SM bits of EIMOD0 register since the sampling clock stops. When choosing "with sampling"...
  • Page 874 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 19.2.6 "CRC Data Register (CRCDATA)". [ ] Write the CRCDATA register when CRCAEN bit of the CRC mode register (CRCMOD) is "0". Any writing is ignored when the CRCAEN bit is "1".
  • Page 875 ML62Q1000 Series User’s Manual Appendix E. List of Notes Chapter 21 D/A Converter See Section 21.1.3 "List of Pins". [ ] When using the D/A converter, write "0" to the target PnmIE bit and PnmOE bit of port n mode registers (n=0 to 9, A, B，m=0 to 7) to set the general port to Hi-impedance, otherwise a shoot-through...
  • Page 876 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 23.2.5 "SA-ADC Upper/Lower Limit Status Register 1 (SADULS1)". [ ] Do not use bit access instructions and use word or byte access instructions for writing this register. [ ] When using the A/D conversion result upper/lower limit detect function (SALEN bit =1), the interrupt can be cleared by clearing the corresponding bit of SAULS16 or by resetting the LSI.
  • Page 877 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 23.3.3 "A/D Conversion Time Setting". [ ] If choosing to start A/D conversion after discharging the internal sample hold capacitive electrical charge to the VSS level at the start of A/D conversion, the A/D conversion time shown in Table 23-3 and 23-4 is increased by two clocks of the conversion clock (SAD_CLK).
  • Page 878 ML62Q1000 Series User’s Manual Appendix E. List of Notes See Section 25.3.2 "Programming Program Memory Space". [ ] Only erase areas irrelevant to program processing. If erasing the area where program processing is in progress, the LSI works incorrectly. [ ] During block/sector erase, the CPU stops the operation for maximum 50 ms whereas peripheral circuits continue operation.
  • Page 879 Chapter 29 Safety Function See Section 29.3.2 "Unused ROM Area Access Reset Function". [ ] CSR[3] is unused on the ML62Q1000 series. The data of CSR "0x8 to 0xF" are handled as "0x0 to 0x7". See Section 29.3.3 "Clock Mutual Monitoring Function".
  • Page 880 ML62Q1000 Series User’s Manual Appendix E. List of Notes Appendix A Register List (SFR List) [ ] Note there are some SFRs that has undefined initial value. Appendix B Package Dimensions Notes for Mounting the Surface Mount Type Package [ ] The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

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  • Page 882 ML62Q1000 Series User’s Manual Revision History REVISION HISTORY Page Document Date Description Previous Current Edition Edition FEUL62Q1000-01 2018.12.11 ML62Q1300/1500/1700 Integrated First Edition FEUL62Q1000...

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