LAPIS Semiconductor ML62Q1000 Series User Manual page 667

22.3.1.1 Reset Output
Figure 22-3 shows the operation timing chart when the VLS0 reset output without sampling is specified.
VLS0EN bit
Threshold voltage (at rise)
VLS0 comparator
comparison result
VLS0 reset
Figure 22-3 Operation Timing Chart When the VLS0 Reset Output without Sampling is specified
The operation shown in Figure 22-3 is described below:
(1) Choose a detection voltage by the VLS0LV3 to VLS0LV0 bits of the VLS0LV register.
(2) Choose "without sampling" by the VLS0SM1 and VLS0SM0 bits of the VLS0SMP register.
(3) Write "0x02" or "0x03" to VLS0AMD[1:0] bits of VLS0MOD register in order to choose the supervisor mode.
(4) Choose an operation function by the VLS0SEL1 and VLS0SEL0 bits of the VLS0MOD register.
(5) Set the VLS0EN bit of the VLS0CON register to "1" (VLS0 starts operation in the supervisor mode).
(6) After approximately 300 μs (approx. 300 μs + sampling clock cycle x 3 when sampling is enabled) passed, the
detection result of VLS0 becomes stabilized and the VLS0RF bit of the VLSCON register is set to "1" (value of the
voltage level supervisor bit (VLS0F) is read in software) (*
(7) When the power voltage (V
the VLS0 interrupt or VLS0 reset.
(8) If V becomes equal to or above the threshold voltage (V
DD
reset.
(9) Write "0" to the VLS0EN bit to disable VLS0 operation.
1
* : VLS0F bit/interrupt/reset is masked until the VLS0RF bit becomes "1".
FEUL62Q1000
(1)~(5)
↓
VLS0RF
V
DD
(at fall)
Stabilization
VLS0F
) becomes below the threshold voltage V
DD
(6) (7)
↓ ↓
time
1
).
), the VLS0F bit is cleared to "0" to release the VLS0
VLSR
ML62Q1000 Series User's Manual
Chapter 22 Voltage Level Supervisor
(8)
↓
V
VLSR
V
VLSF
V
SS
, the VLS0F bit is set to "1" to generate
VLSF
(9)
↓
22-12