AT&T 3B2/300 Technical Reference Manual page 533

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
Control Status Register
The CM527 A Card contains a 16-bit Control Status Register (CSR) used to control and monitor
certain CM527 A functions. Each bit is readable/writable. During the read operation, it is output to the
bus as 32 bits with the upper 16 bits unknown.
The write operation will only write the specified bit. The CM527 A Card CSR bits are defined in
the following table.
CM527 A CONTROL ST A TUS REGISTER
BIT DESCRIPTION
15 RESERVED: This bit is reserved for future needs. This bit will always return a "O" and can
not be modified.
14
VCOFF: When set, the virtual cache is turned OFF. This bit is both set and cleared under
program control. After a powerup reset, this bit is set. Also, two CSR addresses are provided
to flush the entire virtual cache (Ox10044) or flush the data section of the virtual cache
(Oxl0048).
13
ADPINT15: This bit is set under program control. When set, a level 15 interrupt will be
generated to the MPE card CPU. It must be cleared under program control. After powerup
reset, this bit is indeterminate.
12 RESERVED: This bit is reserved for future needs. This bit will always return a "O" and can
not be modified.
11 ALFLT: This bit is set by hardware when the MPE card encounters an alignment fault
condition. It is cleared under program control. After a powerup reset, the state of this bit is
indeterminate.
4-10 RESERVED: These bits and their corresponding addresses are reserved for the BUB Common
Interface. They will always be returned as "O" when read.
03 ERROR: This bit should be set whenever the MPE card generates or detects any error
condition on the BUB. Since the MPE card does not generate BFLTO or BFAILO, it is only set
by hardware when the MPE card encounters a fault on the BUB when it is accessing main
memory. Note that in the case of a BUB fault while the MPE card is accessing memory, an
external memory exception will be generated to the MPE card CPU. This bit is cleared under
program control. After powerup reset, the state of this bit is indeterminate.
02
OPINT15: This bit can be set under program control. When set, it will cause a level 15
interrupt to be sent over the BUB to the system CPU. The bit is also cleared under program
control. After a powerup reset, this bit will be cleared.
01
HALT: This bit is automatically set on MPE card reset, causing the MPE card processor to
remain in a quiescent state until the bit is cleared under program control. In addition, this bit
can be set under program control. This will provide the system with a means to
synchronously inhibit the MPE card from accessing the BUB. Clearing the bit after being set
will allow the MPE card to start execution where it left off when it was set. (Note that the BUB
connector inhibit will turn off the board asynchronously and should not be used during normal
operation.)
00 RESET: This bit can be written under program control to reset the MPE card. It is
automatically cleared on uMPB reset.
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