AT&T 3B2/300 Technical Reference Manual page 355

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
PS
CACHEABLE
REFERENCED
MODIFIED
Bits 04-03 are the Page Size (PS) bits. These bits determine the page size for the
MMU operations as follows:
BIT 04 BIT 03 PAGE SIZE
0 0 2 Kilobytes
0 1 4 Kilobytes
1 0 8 Kilobytes
1 1 RESERVED
Bit 02 is the Cacheable bit. The Cacheable ($) bit determines the state of CABLE
during misprocessing and updating of the Referenced and Modified bits. (If $=0,
then CABLE =1; if $=1, then CABLE =0.)
Bit 01 is the Referenced (R) bit. The R bit in the segment descriptor is set (R=l)
when the segment descriptor is brought into the segment descriptor cache as a
result of misprocessing. When R=O, the R bit in the segment descriptor is not
updated.
Bit 00 is the Modified (M) bit. If M=l, the segment descriptor M bit is updated on
the first write to a segment.
Flush ID Number Register
The Flush ID Number Register (FIDNR) is used in multiple context only. Writing the address of the
SOT to the FIDNR causes all page descriptor cache entries associated with the flushed ID to be flushed
from the PDC and SOC. The format of the FIDNR is as follows.
FLUSH ID NUMBER REGISTER
BITS 31-03 02-00
FIELD SDT ADDRESS RESERVED
3-102 TECHNICAL REFERENCE MANUAL