AT&T 3B2/300 Technical Reference Manual page 377

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
Interrupt Assignments.
Figure 3-35 defines the interrupt levels for the various interrupt sources.
When a 3B2 Enhanced Input/Output (EIO) bus peripheral and a Buffered Microbus (BUB) peripheral
interrupt the CPU at the same time and same level, the system board will pass the CPU interrupt
acknowledge to the 1/0 peripheral. The 382 EIO bus has priority over the BUB for equal interrupts.
NOTES:
VERSION 3 SYSTEM BOARD INTERRUPT ASSIGNMENTS
LEVEL VECTOR SOURCE
NMI
00 ABORT SWITCH ACTIVATION (NOTE 1)
NMI 00 SANITY TIMER EXPIRATION (NOTE 1)
NMI 00 THERMAL SHUTDOWN (NOTE 1)
15
15 UNIX INTERVAL TIMER TIMEOUT
15 15 POWER DOWN REQUEST
15 15 UBUS OR BUB OPERATIONAL INTERRUPT
15 15 SINGLE BIT MEMORY ERROR
15 15 MULTIPLE BIT MEMORY ERROR
15 15
UBUS, BUB, EIO BUS RECEIVED FAIL
15 15 UBUS TIMER TIMEOUT
14 (NOTE 2) BUB (REAL TIME INTERRUPT)
13 13 DUART AND DUART OMA COMPLETE
12 (NOTE 2) BUB (BLOCK)
11 11 FLOPPY AND FLOPPY OMA COMPLETE
10
(NOTE 2) BUB (CHARACTER)
9 9
PIR-9 (FROM CSER)
8 8 PIR-8 (FROM CSER)
1.
Vector 00 is provided by internal CPU operation.
2. First level interrupt vector provided by system board
hardware; second level by peripheral.
LEGEND:
CSER Control, Status, and Error Register
DMA Direct Memory Access
NMI Nonmaskable Interrupt
PIR Programmed Interrupt Request
DUART Dual Universal Asynchronous Receiver/Transmitter
Figure 3-35: Version 3 System Board Interrupt Assignments
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