AT&T 3B2/300 Technical Reference Manual page 330

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
SIZE BIT ADDRESS BITS DAT A STROBES V AUD DAT A BYTES
32-BIT 16-BIT
PSIZE16[0) PPAOl[l] PPAOO[l) PDSO[O] PDSl[O)
MAIN MEMORY INPUT /OUTPUT BUS
16 BIT
0 0
X
0 0 0 AND 1 0 AND 1
0 0
X
0 1
0 0
0 0
X
1 0 1 1
0 0
X
1 1 ILLEGAL
-
0 1
X
0
0
2 AND 3
0 AND 1
0 1
X
0 1 0 OR 2
0
0 1
X
1 0 1 OR 3 1
0 1
X
1 1 ILLEGAL
-
8 BIT
1 0 0
X
0 0 1
1 0 1
X
0 1
1
1 1 0
X
0 2 1
1 1 1
X
0 3 1
LEGEND:
x Don't care bit
Figure 3-25: Data Byte Selection Summary
Parity Generation and Checking. Four parity bits (MP AR3-0(1]) are generated for each of the
four data bytes. Parity is checked only as part of read operations. If bad parity is detected, the
Peripheral Fault (PFLT(O]) and Memory Parity Error (MP ARER[O]) signals are asserted to the system
board CPU or peripheral controllers (feature cards) depending on the type of access.
Bypass Logic. The Bypass Logic is used to establish direct communication between the system
board CPU and feature cards without having to go through the main memory. Hence the term
"bypass" is used to mean that main memory is bypassed for system board-feature card direct
communication. The Bypass Logic passes the low order 24 bits of the Address Bus and the lower order
16 bits of the data bus directly to the 1/0 bus during direct communication between CPU and feature
cards.
The system board requests the "bypass" mode by asserting the composite Input/Output Chip Select
signal (CREQ[O]).
FUNCTIONAL DESCRIPTION 3-77