AT&T 3B2/300 Technical Reference Manual page 299

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
Segment Descriptor Cache. The Segment Descriptor Cache (SDC) consists of 32 descriptors. Each
descriptor is 64 bits in length and is divided into four parts (sections).
Page Descriptor Cache. The Page Descriptor Cache (PDC) consists of sixty-four 64-bit descriptors
organized in a 2-way set-associative configuration. The PDC is divided into four parts which
correspond to the four sections of virtual memory.
Section Random Access Memories.
The MMU contains two Random Access Memory (RAM)
areas called Section RAM A (SRAMA) and Section RAM B (SRAMB). Each of these areas contain four
32-bit words. SRAMA bits 31-05 describes the base address of the Segment Descriptor Table (SDI)
for each of the four sections of virtual memory. SRAMB bits 22-10 describes the length (number of
entries) in the SDI for each of the four sections of virtual memory. The contents of SRAMA (4 words)
and SRAMB (4 words) are part of the error report output by the
/etc/errdump command. The SRAMA
and SRAMB are identified as "srama" and "sramb" in the error report. The format of SRAMA and
SRAMB are as follows.
SECTION RAM A (SRAMA)
BITS 31 - 05 04 - 00
FIELD SDT ADDRESS RESERVED
SECTION RAM B (SRAMB)
BITS 31 - 23 22 - 10 09 - 00
FIELD RESERVED SOT LENGTH RESERVED
MMU Registers. The MMU contains four 32-bit registers:
• Configuration Register (CR)
• Virtual Address Register (VAR)
• Fault Code Register (FLTCR)
• Fault Address Register (FLT AR).
These registers are used to store MMU state information. The contents of FLT AR and FL TCR are
part of the error report output by the
/etc/errdump command. The FLTAR and FLTCR are identified
as "fltar" and "fltcr" in the error report.
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