AT&T 3B2/300 Technical Reference Manual page 269

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
PINT2-0[0]
feature cards. The Peripheral Bus Acknowledge Input (PBACKI) enters a feature
card. The PBACKO exits a feature card. The first feature card in the chain (feature
card slot 1 to n) wanting bus access inhibits the propagation of the acknowledge
signal and asserts a PBUSY[O] signal.
Three peripheral interrupt signals are logically OR' ed from all input/ output bus
devices (PINT2-0[0]). A feature card connects to only one of these three
interrupts. PINT2 is the highest priority of the three interrupts. A feature card
asserts the appropriate PINT signal to request an interruption of the system board
CPU (request for service). PINT2 is reserved for use by AT&T designs.
PIAKI2-0[0]/PIAK02-0[0]
PFAIL[O]
PFLT[O]
The system board CPU asserts the appropriate Peripheral Interrupt Acknowledge
(PIAK2-0[0]) signal to respond to the receipt of a Peripheral Interrupt (PINT)
request. The acknowledge signals are daisy-chained through all feature cards. The
Peripheral Interrupt Acknowledge Input (PIAKI) signal enters a feature card. The
Peripheral Interrupt Acknowledge Output (PIAKO) signal exits a feature card. A
feature card requesting an interrupt of the system board CPU inhibits the
propagation of the interrupt acknowledge signal and asserts a Peripheral Data
Acknowledge (PDTACK[O]) signal during the normal bus protocol operation.
The Peripheral Fail (PFAIL) signal is asserted by a feature card to report a failure on
the card.
The Peripheral Fault (PFL T) signal is asserted by the bus slave to report the
detection of an erroneous condition during an
1/0
bus cycle (for example, bus
time-out).
MOS Data Bus.
The ED-4C637-30 system board buffers the lower 8 bits of the
1/0
data bus
(D07-00[l]) to create an MOS Data Bus. The MOS Data Bus serves the low power devices that cannot
drive the TTL inputs over the entire data bus. The MOS Data Bus serves the following:
• Read Only Memory (ROM)
• Timers
• Time-of-Day (TOD) Clock
• Nonvolatile Random Access Memory (NVRAM).
The ROM is an exception to the other devices connected to the MOS Data Bus. The ROM also
connects to the data bus bits 31-08; however, only data bus bits 07-00 are connected via the MOS
Data Bus (buffered).
Data Transfers
Data transfers can be categorized into the following operations:
• Main memory read operation by a feature card
• Main memory write operation by a feature card
• Feature card read operation by the system board
• Feature card write operation by the system board.
3-16 TECHNICAL REFERENCE MANUAL