AT&T 3B2/300 Technical Reference Manual page 363

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
RC Bits 23 and 22 are the Round Control (RC) mode bits. The decode of these bits is
as follows.
BIT 23 BIT 22
DESCRIPTION
0 0 ROUND TO NEAREST
0 1 ROUND TOW ARDS PLUS INFINITY
1 0 ROUND TOW ARDS MINUS INFINITY
1 1
ROUND TOWARDS ZERO (TRUNCATION)
N Bit 21 is the Negative (N) condition bit. Bit 21 is set [1] when result of the last
operation is negative. Bit 21 is cleared when the result of the last operation is
positive.
Z Bit 20 is the Zero (Z) condition bit. Bit 20 is set [1] when the result of the last
operation is zero. Bit 20 is cleared when the result of the last operation is nonzero.
IO Bit 19 is the Integer Overflow (IO) bit. Bit 19 is set [1] when a convert float to
integer operation causes an overflow.
PS Bit 18 is the Inexact Sticky (PS) bit. Bit 18 is set [1] when the result of an operation
cannot be specified in the destination format. Bit 18 is cleared on reset.
CSC Bit 17 is the Context Switch Control (CSC) bit. Bit 17 is set [1] on every MAU
instruction execution. Bit 17 is cleared on reset.
UO Bit 16 is the Unordered (UO) bit. Bit 16 is set [1] when a compare operation results
in an unordered indication; otherwise this bit is cleared. Bit 16 is cleared on reset.
WF Bit 15 is the Write Fault (WF) indicator bit. If enabled (bit 0), this bit is set [1] when
a fault condition occurs during the writing of any result to memory. When this bit
is set, the MAU will not reexecute the operation upon a restart from the CPU.
Instead, it returns a DONE signal and stores the result of the previously faulted
operation in memory.
IM Bit 14 is the Invalid Operation Mask (IM) bit. Bit 14 is set [1] by the user to enable
the generation of an exception when bit 09 (Invalid Operation Sticky bit) is set.
There are no invalid operation exceptions when bit 14 is cleared.
OM Bit 13 is the Overflow Mask (OM) bit. Bit 13 is set [1] by the user to enable the
generation of an exception when bit 08 (Overflow Sticky bit) is set. There are no
overflow exceptions when bit 13 is cleared.
UM Bit 12 is the Underflow Mask (UM) bit. Bit 12 is set [1] by the user to enable the
generation of an exception when bit 07 (Underflow Sticky bit) is set. There are no
underflow exceptions when bit 12 is cleared.
QM Bit 11 is the Divide by Zero Mask (QM) bit. Bit 11 is set [1] by the user to enable
the generation of an exception when bit 06 (Divide by Zero Sticky bit) is set. There
are no divide by zero exceptions when bit 11 is cleared.
PM Bit 10 is the Inexact Mask (PM) bit. Bit 10 is set [1] by the user to enable the
generation of an exception when bit 18 (Inexact Sticky bit) is set [1 ]. There are no
inexact exceptions when bit 10 is cleared.
IS Bit 09 is the Invalid Operation Sticky (IS) bit. Bit 09 is set [1] when a result cannot
be legally stored in a destination, or when illegal operands are given to some
operation.
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