AT&T 3B2/300 Technical Reference Manual page 274

- - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Peripheral Controller Main Memory Read Operation.
Figure 3-8 shows the peripheral controller
main memory read operation. A main memory read by a peripheral controller (feature card) starts with
the feature card asserting an
1/0 bus access request (PBRQ[O]). When the feature card receives the
Peripheral Bus Acknowledge (PBACK[O]), the feature card asserts the Peripheral Bus Busy (PBUSY[O])
signal. The feature card gates the following signals onto the 1/0 bus to start the data transfer:
• Physical Address (P A23-00[l])
• Peripheral Read/Write (PR[l ]W[O]) (1 for read operation)
• Peripheral Size (PSIZE16[0]).
When the address and control signals are stable, the Peripheral Physical Address Strobe (PP AS[O])
and Peripheral Data Strobes (PDSl-0[0]) are asserted. The PBRQ is negated after the data transfer
operation has started (following assertion of the PP AS and negation of PBACK). The assertion of the
Peripheral Data Strobes causes the main memory to gate the read data onto the
1/0 bus. When the
read data is stable, the main memory asserts the Peripheral Data Acknowledge (PDTACK[O]) signal and
the feature card latches the data. The feature card negates the address, strobes, and bus busy signals
and then tri-states the 1/0 bus. The main memory control negates the PDTACK signal and the data
when the data strobes are removed.
FUNCTIONAL DESCRIPTION 3-21