AT&T 3B2/300 Technical Reference Manual page 320

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Control and Status Register
The Control and Status Register (CSR) is a 16-bit register. It provides low-level access to the
system board logic circuits. The CSR controls and monitors various system functions. Certain bits are
written (cleared or set) under software control. Other bits are controlled exclusively by hardware logic.
CSR bits 03 through 00 reflect the state of system board peripheral devices. All CSR bits are readable
by software using either a full or half-word read operation. During a read operation the CSR data is
latched so that it remains constant throughout the read cycle. The CSR is NOT cleared by a hardware
reset. The CSR is bit-addressable for writing. During a software write of the CSR, only one bit at a
time is accessed. The state of the CSR bit after the CSR write operation is dependent only on the
address; the data written is a "don't care" bit. The contents of the CSR are part of the error report
output by the /etc/errdump command. The CSR is identified as "csr" in the error report. The CSR bit
assignments and access information are shown in Figure 3-22.
FUNCTIONAL DESCRIPTION 3-67