AT&T 3B2/300 Technical Reference Manual page 312

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QS
PR
Operand Registers
Bit 06 is the Divide by Zero Sticky (QS) bit. Bit 06 is set
[1]
when the divisor is
normalized zero and the dividend is a finite nonzero number.
Bit 05 is the Partial Remainder (PR) bit. Bit 05 is set [1] when the result of a
remainder operation is a partial remainder. Bit 05 is cleared when the result of a
remainder operation is a full remainder. This bit is cleared on reset.
The MAU contains four operand registers (F3-FO). Each operand register is 80 bits and contains
one operand in an extended format. These registers are accessed via the Data Register in the format of
three 32-bit words. In the peripheral mode, bits 95-80 are ignored during write operations. For read
operations, bits 95-80 are returned as zeros. The operand registers are unchanged on reset. The
contents of these registers are indeterminate on powerup. The format of each of the four operand
registers is as follows.
OPERAND REGISTERS (F3- FO)
BITS 95 - 80
79 78 - 64 63
62 - 00
FIELD UNUSED SIGN EXPONENT
J
FRACTION
The operand register fields are defined in the following paragraphs.
UNUSED
SIGN
EXPONENT
J
FRACTION
Bits 95-80 are not used. These bits are returned as zeros for a read operation.
Bit 79 is the SIGN bit. When set
[1]
the sign is negative; cleared represents a
positive value.
Bits 78-64 are used as the EXPONENT field. The exponent is biased by 16,383.
Bit 63 is the Explicit (J) bit. The
J
bit is to the left of the binary point in the 2°
position. In combination, the
J
bit and the FRACTION field can represent values in
the range O to 2-(2-
63 ).
Bits 62-00 are used to represent the fractional part of a number.
FUNCTIONAL DESCRIPTION 3-59