AT&T 3B2/300 Technical Reference Manual page 521

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
Control Status Register
The CM524A Card contains a 16-bit Control Status Register (CSR) used to control and monitor
certain CM524A functions. Each bit is readable/writable. During the read operation, it is output to the
bus as 32 bits with the upper 16 bits unknown.
The write operation will only write the specified bit. The CM524A Card CSR bits are defined in
the following table.
CM524A CONTROL ST A TUS REGISTER
BIT DESCRIPTION
15
ADPINTlO: This bit is set under program control. When set, a level 10 interrupt will be
generated to the PE card CPU. It must be cleared under program control. After a powerup
reset, this bit will be cleared. This bit is required by the common PBus interface.
14 ADPINT12: This bit is set under program control. When set, a level 12 interrupt will be
generated to the PE card CPU. It must be cleared under program control. After a powerup
reset, this bit will be cleared. This bit is required by the common PBus interface.
13
ADPINT15: This bit is set under program control. When set, a level 15 interrupt will be
generated to the PE card CPU. It must be cleared under program control. After a powerup
reset, this bit will be cleared. This bit is required by the common PBus interface.
12 ADPNMI: This bit is set under program control. When set, a nonmaskable interrupt will be
generated to the PE card CPU. It will be cleared through hardware after being acknowledged.
After a powerup reset, this bit will be cleared. This bit is required by the common PBus
interface.
11
ULFLT: This bit is set by hardware when the PE card encounters an alignment fault condition.
It
is cleared under program control. After a powerup reset, the state of this bit is
indeterminate.
4-10
RESERVED: These bits and their corresponding addresses are reserved for the PBus Common
Interface. They will always be returned as unknown when read.
03
ERROR: This bit should be set whenever the PE card generates or detects any error condition
on the PBus. Since the PE card does not generate UFLTO or UFAILO, it is only set by
hardware when the PE card encounters a fault on the BUB when it is accessing main memory.
Note that in the case of a BUB fault while the PE card is accessing memory, an external
memory exception will be generated to the PE card CPU. This bit is cleared under program
control. After a powerup reset, the state of this bit is indeterminate. This bit is required by the
common PBus interface.
02
OPINT15: This bit can be set under program control. When set, it will cause a level 15
interrupt to be sent over the PBus to the system CPU. The bit is also cleared under program
control. After a PE card reset, this bit will be cleared. This bit is required by the common PBus
interface.
01
HALT: This bit is automatically set on PE card reset, causing the PE card processor to remain
in a quiescent state until the bit is cleared under program control. In addition, this bit can be
set under program control. This will provide the system with a means to synchronously
inhibit the PE card from accessing the PBus. Clearing the bit after being set will allow the PE
card to start execution where it left off when it was set. (Note that the PBus connector inhibit
will turn off the board asynchronously and should not be used during normal operation.) This
bit is required by the common PBus interface.
00
RESET: This bit can be written under program control to reset the PE card. It is automatically
cleared on uMPB reset. This bit is required by the common PBus interface.
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